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Simon Schmidt
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edit readme
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2 years ago | |
|---|---|---|
| .vscode | 2 years ago | |
| 4-bit-counter-SV-UVM | 2 years ago | |
| 4-bit-counter-cocotb | 2 years ago | |
| 4-bit-counter-myhdl | 2 years ago | |
| 7Segment_Lattice_ice40_UltraPlus | 2 years ago | |
| LCD_EPD_Simulation_VerilogA | 2 years ago | |
| digitaler-filter-cocotb | 2 years ago | |
| i2c_slave_opencores | 2 years ago | |
| LICENSE | 2 years ago | |
| README.md | 2 years ago | |
README.md
README.md
ESY1B Verifikation mit SystemVerilog und Python
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema “Verifikation mit SystemVerilog und Python”
ESY1A LCD EPaper Modelling with VerilogA
Verwendeter Programmcode in Studienarbeit