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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
12 Commits 1 Branch 0 Tags 2 MiB
Verilog 81.9%
Makefile 6.5%
Python 6.3%
Tcl 3.8%
SystemVerilog 0.8%
Other 0.7%
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Simon 15985de500 edit readme
2021-07-12 00:36:16 +02:00
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LCD_EPD_Simulation_VerilogA added LCD seminararbeit 2021-07-12 00:30:42 +02:00
LICENSE Initial commit 2021-06-09 08:54:24 +00:00
README.md edit readme 2021-07-12 00:36:16 +02:00

README.md

ESY1B Verifikation mit SystemVerilog und Python

Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"

ESY1A LCD EPaper Modelling with VerilogA

Verwendeter Programmcode in Studienarbeit

i2c project code