Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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Simon Schmidt 15985de500 edit readme 3 months ago
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7Segment_Lattice_ice40_UltraPlus added subfolder 3 months ago
LCD_EPD_Simulation_VerilogA added LCD seminararbeit 3 months ago
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i2c_slave_opencores added i2c example from VL 3 months ago
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README.md edit readme 3 months ago

README.md

ESY1B Verifikation mit SystemVerilog und Python

Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema “Verifikation mit SystemVerilog und Python”

ESY1A LCD EPaper Modelling with VerilogA

Verwendeter Programmcode in Studienarbeit

i2c project code