correct makefile error

2021-06-09 11:15:13 +02:00 · 2021-06-09 11:15:13 +02:00 · 3c2c09f0b9
commit 3c2c09f0b9
parent ec65cf50cb
1 changed files with 1 additions and 1 deletions
--- a/4-bit-counter-cocotb/tests/Makefile
+++ b/4-bit-counter-cocotb/tests/Makefile
@ -32,7 +32,7 @@ TOPLEVEL_LANG ?= verilog
 PWD=$(shell pwd)

 ifeq ($(TOPLEVEL_LANG),verilog)
-    VERILOG_SOURCES = $(PWD)/../hdl/counter.sv
+    VERILOG_SOURCES = $(PWD)/../hdl/counter.v
 else ifeq ($(TOPLEVEL_LANG),vhdl)
    VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
 else