correct makefile error

4-bit-counter-cocotb/tests/Makefile

@@ -32,7 +32,7 @@ TOPLEVEL_LANG ?= verilog
 PWD=$(shell pwd)
 
 ifeq ($(TOPLEVEL_LANG),verilog)
-    VERILOG_SOURCES = $(PWD)/../hdl/counter.sv
+    VERILOG_SOURCES = $(PWD)/../hdl/counter.v
 else ifeq ($(TOPLEVEL_LANG),vhdl)
     VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
 else