added and changed gitignores

4-bit-counter-cocotb/.gitignore

@@ -0,0 +1,15 @@
+__pycache__/
+.vscode/
+
+tests/__pycache__/
+tests/sim_build/
+
+tests/results.xml
+tests/*.swp
+tests/*.vcd
+tests/*.lxt
+
+*.swp
+*.vcd
+*.lxt
+results.xml

4-bit-counter-cocotb/.vscode/settings.json

@@ -1,3 +0,0 @@
-{
-    "python.pythonPath": "/usr/bin/python3"
-}

4-bit-counter-cocotb/tests/dump.vcd

@@ -1,183 +0,0 @@
-$date
-	Tue Jun  8 18:10:07 2021
-$end
-$version
-	Icarus Verilog
-$end
-$timescale
-	1ps
-$end
-$scope module counter $end
-$var wire 1 ! clk $end
-$var wire 4 " data [3:0] $end
-$var wire 1 # load $end
-$var wire 1 $ rst $end
-$var wire 1 % updown $end
-$var reg 4 & data_out [3:0] $end
-$upscope $end
-$enddefinitions $end
-#0
-$dumpvars
-bx &
-z%
-z$
-z#
-bz "
-1!
-$end
-#5000000
-0!
-#10000000
-1$
-1!
-#15000000
-0!
-#20000000
-b0 &
-1!
-#25000000
-0!
-#30000000
-1!
-#35000000
-0!
-#40000000
-1!
-#40000001
-0$
-1#
-b1110 "
-#45000001
-0!
-#50000001
-b1110 &
-1!
-#55000001
-0!
-#55000002
-b0 &
-1$
-0#
-1%
-b1100 "
-1!
-#60000002
-0$
-0!
-#65000002
-b1 &
-1!
-#70000002
-0!
-#75000002
-b10 &
-1!
-#80000002
-0!
-#85000002
-b11 &
-1!
-#90000002
-0!
-#95000002
-b100 &
-1!
-#100000002
-0!
-#105000002
-b101 &
-1!
-#110000002
-0!
-#115000002
-b110 &
-1!
-#120000002
-0!
-#125000002
-b111 &
-1!
-#130000002
-0!
-#135000002
-b1000 &
-1!
-#140000002
-0!
-#145000002
-b1001 &
-1!
-#150000002
-0!
-#155000002
-b1010 &
-1!
-#160000002
-0!
-#160000003
-b0 &
-1$
-0%
-b1110 "
-1!
-#165000003
-0$
-1#
-0!
-#170000003
-b1110 &
-1!
-#175000003
-0#
-0!
-#180000003
-b1101 &
-1!
-#185000003
-0!
-#190000003
-b1100 &
-1!
-#195000003
-0!
-#200000003
-b1011 &
-1!
-#205000003
-0!
-#210000003
-b1010 &
-1!
-#215000003
-0!
-#220000003
-b1001 &
-1!
-#225000003
-0!
-#230000003
-b1000 &
-1!
-#235000003
-0!
-#240000003
-b111 &
-1!
-#245000003
-0!
-#250000003
-b110 &
-1!
-#255000003
-0!
-#260000003
-b101 &
-1!
-#265000003
-0!
-#270000003
-b100 &
-1!
-#275000003
-0!
-#275000004

4-bit-counter-cocotb/tests/results.xml

@@ -1,9 +0,0 @@
-<testsuites name="results">
-  <testsuite name="all" package="all">
-    <property name="random_seed" value="1623168607" />
-    <testcase name="test_counter_reset" classname="test_counter" file="/home/sim/ice40/sta/4-bit-counter-cocotb/tests/test_counter.py" lineno="7" time="0.0012416839599609375" sim_time_ns="40000.001" ratio_time="32214317.241609827" />
-    <testcase name="test_counter_load" classname="test_counter" file="/home/sim/ice40/sta/4-bit-counter-cocotb/tests/test_counter.py" lineno="25" time="0.0005171298980712891" sim_time_ns="15000.001000000004" ratio_time="29006253.662657455" />
-    <testcase name="test_counter_inc" classname="test_counter" file="/home/sim/ice40/sta/4-bit-counter-cocotb/tests/test_counter.py" lineno="41" time="0.0017952919006347656" sim_time_ns="105000.00099999999" ratio_time="58486311.31398459" />
-    <testcase name="test_counter_dec" classname="test_counter" file="/home/sim/ice40/sta/4-bit-counter-cocotb/tests/test_counter.py" lineno="67" time="0.0019235610961914062" sim_time_ns="115000.00100000002" ratio_time="59784948.46235797" />
-  </testsuite>
-</testsuites>

4-bit-counter-cocotb/tests/sim_build/cmds.f

@@ -1 +0,0 @@
-+timescale+1ns/1ps

4-bit-counter-cocotb/tests/sim_build/sim.vvp

@@ -1,79 +0,0 @@
-#! /usr/local/bin/vvp
-:ivl_version "12.0 (devel)" "(s20150603-1130-g1f8876be)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 12;
-:vpi_module "/usr/local/lib/ivl/system.vpi";
-:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
-:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
-:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
-:vpi_module "/usr/local/lib/ivl/va_math.vpi";
-:vpi_module "/usr/local/lib/ivl/v2009.vpi";
-S_0x55fb04b57e00 .scope package, "$unit" "$unit" 2 1;
- .timescale -9 -12;
-S_0x55fb04b57f90 .scope module, "counter" "counter" 3 5;
- .timescale -9 -12;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "rst";
-    .port_info 2 /INPUT 4 "data";
-    .port_info 3 /INPUT 1 "updown";
-    .port_info 4 /INPUT 1 "load";
-    .port_info 5 /OUTPUT 4 "data_out";
-o0x7f9f460c2018 .functor BUFZ 1, C4<z>; HiZ drive
-v0x55fb04b7dc80_0 .net "clk", 0 0, o0x7f9f460c2018;  0 drivers
-o0x7f9f460c2048 .functor BUFZ 4, C4<zzzz>; HiZ drive
-v0x55fb04ba0930_0 .net "data", 3 0, o0x7f9f460c2048;  0 drivers
-v0x55fb04ba0a10_0 .var "data_out", 3 0;
-o0x7f9f460c20a8 .functor BUFZ 1, C4<z>; HiZ drive
-v0x55fb04ba0ad0_0 .net "load", 0 0, o0x7f9f460c20a8;  0 drivers
-o0x7f9f460c20d8 .functor BUFZ 1, C4<z>; HiZ drive
-v0x55fb04ba0b90_0 .net "rst", 0 0, o0x7f9f460c20d8;  0 drivers
-o0x7f9f460c2108 .functor BUFZ 1, C4<z>; HiZ drive
-v0x55fb04ba0ca0_0 .net "updown", 0 0, o0x7f9f460c2108;  0 drivers
-E_0x55fb04b905c0 .event posedge, v0x55fb04b7dc80_0;
-    .scope S_0x55fb04b57f90;
-T_0 ;
-    %wait E_0x55fb04b905c0;
-    %load/vec4 v0x55fb04ba0b90_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.0, 8;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v0x55fb04ba0a10_0, 0;
-    %jmp T_0.1;
-T_0.0 ;
-    %load/vec4 v0x55fb04ba0ad0_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.2, 8;
-    %load/vec4 v0x55fb04ba0930_0;
-    %assign/vec4 v0x55fb04ba0a10_0, 0;
-    %jmp T_0.3;
-T_0.2 ;
-    %load/vec4 v0x55fb04ba0ca0_0;
-    %flag_set/vec4 8;
-    %jmp/0 T_0.4, 8;
-    %load/vec4 v0x55fb04ba0a10_0;
-    %addi 1, 0, 4;
-    %jmp/1 T_0.5, 8;
-T_0.4 ; End of true expr.
-    %load/vec4 v0x55fb04ba0a10_0;
-    %subi 1, 0, 4;
-    %jmp/0 T_0.5, 8;
- ; End of false expr.
-    %blend;
-T_0.5;
-    %assign/vec4 v0x55fb04ba0a10_0, 0;
-T_0.3 ;
-T_0.1 ;
-    %jmp T_0;
-    .thread T_0;
-    .scope S_0x55fb04b57f90;
-T_1 ;
-    %vpi_call/w 3 25 "$dumpfile", "dump.vcd" {0 0 0};
-    %vpi_call/w 3 26 "$dumpvars", 32'sb00000000000000000000000000000001, S_0x55fb04b57f90 {0 0 0};
-    %end;
-    .thread T_1;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "-";
-    "/home/sim/ice40/cocotb/examples/4-bit-counter/tests/../hdl/counter.sv";

4-bit-counter-myhdl/.gitignore

@@ -0,0 +1,6 @@
+__pycache__/
+.vscode/
+
+*.swp
+*.vcd
+*.lxt

4-bit-counter-myhdl/.vscode/settings.json

@@ -1,3 +0,0 @@
-{
-    "python.pythonPath": "/usr/bin/python3"
-}

4-bit-counter-myhdl/tb_counter_4bit.vvp

@@ -1,88 +0,0 @@
-#! /usr/local/bin/vvp
-:ivl_version "12.0 (devel)" "(s20150603-1130-g1f8876be)";
-:ivl_delay_selection "TYPICAL";
-:vpi_time_precision - 11;
-:vpi_module "/usr/local/lib/ivl/system.vpi";
-:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
-:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
-:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
-:vpi_module "/usr/local/lib/ivl/va_math.vpi";
-S_0x556346c658c0 .scope module, "tb_counter_4bit" "tb_counter_4bit" 2 1;
- .timescale -9 -11;
-v0x556346c77d30_0 .var "clk", 0 0;
-v0x556346c77df0_0 .var "data", 3 0;
-v0x556346c77ec0_0 .net "data_out", 3 0, v0x556346c77920_0;  1 drivers
-v0x556346c77fc0_0 .var "load", 0 0;
-v0x556346c78090_0 .var "rst", 0 0;
-v0x556346c78180_0 .var "updown", 0 0;
-S_0x556346c65a50 .scope module, "dut" "counter_4bit" 2 29, 3 8 0, S_0x556346c658c0;
- .timescale -9 -11;
-    .port_info 0 /INPUT 1 "clk";
-    .port_info 1 /INPUT 1 "rst";
-    .port_info 2 /INPUT 4 "data";
-    .port_info 3 /INPUT 1 "updown";
-    .port_info 4 /INPUT 1 "load";
-    .port_info 5 /OUTPUT 4 "data_out";
-v0x556346c51a80_0 .net "clk", 0 0, v0x556346c77d30_0;  1 drivers
-v0x556346c77840_0 .net "data", 3 0, v0x556346c77df0_0;  1 drivers
-v0x556346c77920_0 .var "data_out", 3 0;
-v0x556346c779e0_0 .net "load", 0 0, v0x556346c77fc0_0;  1 drivers
-v0x556346c77aa0_0 .net "rst", 0 0, v0x556346c78090_0;  1 drivers
-v0x556346c77bb0_0 .net "updown", 0 0, v0x556346c78180_0;  1 drivers
-E_0x556346c631d0 .event posedge, v0x556346c51a80_0;
-S_0x556346c518a0 .scope begin, "COUNTER_4BIT_CYCLE" "COUNTER_4BIT_CYCLE" 3 29, 3 29 0, S_0x556346c65a50;
- .timescale -9 -11;
-    .scope S_0x556346c65a50;
-T_0 ;
-    %wait E_0x556346c631d0;
-    %fork t_1, S_0x556346c518a0;
-    %jmp t_0;
-    .scope S_0x556346c518a0;
-t_1 ;
-    %load/vec4 v0x556346c77aa0_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.0, 8;
-    %pushi/vec4 0, 0, 4;
-    %assign/vec4 v0x556346c77920_0, 0;
-    %jmp T_0.1;
-T_0.0 ;
-    %load/vec4 v0x556346c779e0_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.2, 8;
-    %load/vec4 v0x556346c77840_0;
-    %assign/vec4 v0x556346c77920_0, 0;
-    %jmp T_0.3;
-T_0.2 ;
-    %load/vec4 v0x556346c77bb0_0;
-    %flag_set/vec4 8;
-    %jmp/0xz  T_0.4, 8;
-    %load/vec4 v0x556346c77920_0;
-    %addi 1, 0, 4;
-    %assign/vec4 v0x556346c77920_0, 0;
-    %jmp T_0.5;
-T_0.4 ;
-    %load/vec4 v0x556346c77920_0;
-    %subi 1, 0, 4;
-    %assign/vec4 v0x556346c77920_0, 0;
-T_0.5 ;
-T_0.3 ;
-T_0.1 ;
-    %end;
-    .scope S_0x556346c65a50;
-t_0 %join;
-    %jmp T_0;
-    .thread T_0;
-    .scope S_0x556346c658c0;
-T_1 ;
-    %vpi_call 2 13 "$from_myhdl", v0x556346c77d30_0, v0x556346c78090_0, v0x556346c77df0_0, v0x556346c78180_0, v0x556346c77fc0_0 {0 0 0};
-    %vpi_call 2 20 "$to_myhdl", v0x556346c77ec0_0 {0 0 0};
-    %vpi_call 2 25 "$dumpfile", "tb_counter_4bit.lxt" {0 0 0};
-    %vpi_call 2 26 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x556346c658c0 {0 0 0};
-    %end;
-    .thread T_1;
-# The file index is used to find the file name in the following table.
-:file_names 4;
-    "N/A";
-    "<interactive>";
-    "tb_counter_4bit.v";
-    "counter_4bit.v";

digitaler-filter-cocotb/.gitignore

@@ -1,5 +1,8 @@
 __pycache__/
-*swp
-*vcd
+
+*.swp
+*.vcd
+*.lxt
+
 results.xml
 sim_build