schmidtsi76327
/
ESY1A_B_Seminararbeiten
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
8 Commits
1 Branch
Tree: a0491ca1c6
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'a0491ca1c6'
${ noResults }
ESY1A_B_Seminararbeiten/4-bit-counter-SV-UVM/sim/.gitignore

.gitignore 93B
Raw Normal View History

add SV example
3 years ago
​
​
​
​
​
​
​
​
​
 12345678910 
  1. modelsim.*

  2. transcript* 

  3. vlog.* 

  4. work/

  5. counter_cov* 

  6. fcover* 

  7. covhtml* 

  8. vcover* 

  9. *.log

  10. *.wlf