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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/README.md

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added i2c example from VL
2 years ago
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  1. # i2c_slave_opencores

  2. 

  3. I2C Verilog Testbench für einen CO2 Sensor

  4. 

  5. Beispiel ist von OpenCores

  6. 

  7. https://git.efi.th-nuernberg.de/gitea/schmidtsi76327/i2c_slave_opencores