initial commit

4-bit-counter-myhdl/.vscode/settings.json

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+{
+    "python.pythonPath": "/usr/bin/python3"
+}

4-bit-counter-myhdl/counter_4bit.v

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+// File: counter_4bit.v
+// Generated by MyHDL 0.11
+// Date: Mon Jun  7 19:39:23 2021
+
+
+`timescale 1ns/10ps
+
+module counter_4bit (
+    clk,
+    rst,
+    data,
+    updown,
+    load,
+    data_out
+);
+
+
+input clk;
+input rst;
+input [3:0] data;
+input updown;
+input load;
+output [3:0] data_out;
+reg [3:0] data_out;
+
+
+
+
+always @(posedge clk) begin: COUNTER_4BIT_CYCLE
+    if (rst) begin
+        data_out <= 0;
+    end
+    else if (load) begin
+        data_out <= data;
+    end
+    else begin
+        if (updown) begin
+            data_out <= (data_out + 1);
+        end
+        else begin
+            data_out <= (data_out - 1);
+        end
+    end
+end
+
+endmodule

4-bit-counter-myhdl/counter_4bit_conv.py

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+import myhdl
+from myhdl import *
+
+@block
+def counter_4bit(clk, rst, data, updown, load, data_out):
+
+    @always(clk.posedge)
+    def cycle():
+        if rst:
+            data_out.next = 0
+        elif load:
+            data_out.next = data
+        else:
+            if updown:
+                data_out.next = data_out + 1
+            else:
+                data_out.next = data_out - 1
+
+    return cycle
+
+
+def convert():
+    clk = Signal(bool(0))
+    rst = Signal(bool(0)) # nur sync reset hier
+    # reset = ResetSignal(0, active=0, isasync=True)
+    updown = Signal(bool(0))
+    load = Signal(bool(0))
+    data = Signal(modbv(val=0, min=0, max=15)[4:])
+    data_out = Signal(modbv(val=0, min=0, max=15)[4:])
+
+    inst = counter_4bit(clk, rst, data, updown, load, data_out)
+    inst.convert(hdl='Verilog')
+    # inst.convert(hdl='VHDL')

4-bit-counter-myhdl/counter_4bit_tb.py

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+import os
+import myhdl
+from myhdl import *
+
+
+module = 'counter_4bit'
+testbench = 'tb_%s' % module
+
+build_cmd = "iverilog -o %s.vvp %s.v %s.v" % (testbench, module, testbench)
+
+
+def tb_counter_4bit():
+    clk = Signal(bool(0))
+    rst = Signal(bool(0))
+    updown = Signal(bool(0))
+    load = Signal(bool(0))
+    data = Signal(modbv(val=0, min=0, max=15)[4:])
+    data_out = Signal(modbv(val=0, min=0, max=15)[4:])
+
+    # DUT
+    print(build_cmd)
+    if os.system(build_cmd):
+        raise Exception("Error running build command")
+
+    dut = Cosimulation(
+        "vvp -m myhdl %s.vvp -lxt2" % testbench,
+        clk=clk,
+        rst=rst,    
+        updown=updown,
+        load=load,
+        data=data,
+        data_out=data_out
+    )
+
+    @always(delay(4))
+    def clkgen():
+        clk.next = not clk
+
+    @instance
+    def check():
+        print("initialize")
+        clk.next = 0
+        rst.next = 0
+        load.next = 0
+        updown.next = 1
+        data.next = 0
+        
+        yield clk.posedge
+        yield clk.posedge
+
+        print("... OK")
+        print("test 1: reset")
+        yield clk.negedge
+        rst.next = 1
+        yield clk.posedge
+        yield clk.negedge
+        rst.next = 0
+        yield clk.posedge
+        
+        assert data_out == 0, f"assert failed with data_out {data_out} != 0"
+
+        yield clk.posedge
+        yield clk.posedge
+
+        
+        print("... OK")
+        print("test 2: load")
+
+        yield clk.posedge
+        load.next = 1
+        data.next = Signal(modbv(13)[4:])
+        yield clk.negedge
+        yield clk.posedge
+        yield clk.negedge
+        assert data_out == 13, f"assert failed with data_out {data_out} != {13}"
+
+        load.next = 0
+        yield clk.posedge
+        yield clk.negedge
+
+
+        print("... OK")
+        print("test 3: inc")
+
+        yield clk.negedge
+        rst.next = 1
+        yield clk.posedge
+        yield clk.negedge
+        rst.next = 0
+        soll = 0
+
+        for i in range(4):
+            assert data_out == soll, f"assert failed with data_out {int(data_out)} != {i}"
+
+            yield clk.posedge
+            soll += 1
+            yield clk.negedge
+
+        print("... OK")
+        print("test 4: dec")
+
+        soll = 13
+
+        yield clk.posedge
+        updown.next = 0
+        load.next = 1
+        data.next = Signal(modbv(soll)[4:])
+        yield clk.negedge
+        yield clk.posedge
+        yield clk.negedge
+        load.next = 0
+
+        for i in range(4):
+            assert data_out == soll, f"assert failed with data_out {int(data_out)} != {soll}"
+
+            yield clk.posedge
+            soll -= 1
+            yield clk.negedge
+
+
+        print("... OK")
+
+        for _ in range(10):
+            yield clk.posedge
+
+        raise StopSimulation
+
+    return instances()
+
+
+def simulate():
+    sim = Simulation(tb_counter_4bit())
+    sim.run()

4-bit-counter-myhdl/counter_reference.v

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+//////////////////////////////////////////////////////////////
+//  4-bit loadable up-down counter          //////
+//////////////////////////////////////////////////////////////
+
+module counter(clk, rst, data, updown, load, data_out);
+
+    input clk, rst, load;
+    input updown;
+    input [3:0] data;
+
+    output reg [3:0] data_out;
+
+    always @(posedge clk)
+    begin
+        if(rst)
+            data_out <= 4'b0;
+        else if(load)
+            data_out <= data;
+        else
+            data_out <= ((updown)?(data_out + 1'b1):(data_out -1'b1));
+    end
+
+endmodule

4-bit-counter-myhdl/main.py

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+import counter_4bit_conv, counter_4bit_tb
+import os
+
+# print("Konvertiere MyHDL Design in Verilog")
+# counter_4bit_conv.convert()
+
+print("Simuliere Verilog Design mit MyHDL")
+counter_4bit_tb.simulate()
+
+os.system("gtkwave.exe -S run.tcl *.lxt")

4-bit-counter-myhdl/run.tcl

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+### --------------------------------------------------------------------
+### gtkwave.tcl
+### Author: Simon Schmidt
+### --------------------------------------------------------------------
+
+# Resources:
+# Manual: http://gtkwave.sourceforge.net/gtkwave.pdf#Appendix-E-Tcl-Command-Syntax
+
+# Add all signals
+set nfacs [ gtkwave::getNumFacs ]
+
+set all_facs [list]
+for {set i 0} {$i < $nfacs } {incr i} {
+    set facname [ gtkwave::getFacName $i ]
+    lappend all_facs "$facname"
+}
+
+set num_added [ gtkwave::addSignalsFromList $all_facs ]
+puts "num signals added: $num_added"
+
+# zoom full
+gtkwave::/Time/Zoom/Zoom_Full

4-bit-counter-myhdl/tb_counter_4bit.v

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+module tb_counter_4bit;
+
+reg clk;
+reg rst;
+reg [3:0] data;
+reg updown;
+reg load;
+wire [3:0] data_out;
+
+
+
+initial begin
+    $from_myhdl(
+        clk,
+        rst,
+        data,
+        updown,
+        load
+    );
+    $to_myhdl(
+        data_out
+    );
+    
+    // dump file
+    $dumpfile("tb_counter_4bit.lxt");
+    $dumpvars(0, tb_counter_4bit);
+end
+
+counter_4bit dut(
+    clk,
+    rst,
+    data,
+    updown,
+    load,
+    data_out
+);
+
+endmodule

4-bit-counter-myhdl/tb_counter_4bit.vvp

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+#! /usr/local/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1130-g1f8876be)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 11;
+:vpi_module "/usr/local/lib/ivl/system.vpi";
+:vpi_module "/usr/local/lib/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/local/lib/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/local/lib/ivl/v2005_math.vpi";
+:vpi_module "/usr/local/lib/ivl/va_math.vpi";
+S_0x556346c658c0 .scope module, "tb_counter_4bit" "tb_counter_4bit" 2 1;
+ .timescale -9 -11;
+v0x556346c77d30_0 .var "clk", 0 0;
+v0x556346c77df0_0 .var "data", 3 0;
+v0x556346c77ec0_0 .net "data_out", 3 0, v0x556346c77920_0;  1 drivers
+v0x556346c77fc0_0 .var "load", 0 0;
+v0x556346c78090_0 .var "rst", 0 0;
+v0x556346c78180_0 .var "updown", 0 0;
+S_0x556346c65a50 .scope module, "dut" "counter_4bit" 2 29, 3 8 0, S_0x556346c658c0;
+ .timescale -9 -11;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /INPUT 4 "data";
+    .port_info 3 /INPUT 1 "updown";
+    .port_info 4 /INPUT 1 "load";
+    .port_info 5 /OUTPUT 4 "data_out";
+v0x556346c51a80_0 .net "clk", 0 0, v0x556346c77d30_0;  1 drivers
+v0x556346c77840_0 .net "data", 3 0, v0x556346c77df0_0;  1 drivers
+v0x556346c77920_0 .var "data_out", 3 0;
+v0x556346c779e0_0 .net "load", 0 0, v0x556346c77fc0_0;  1 drivers
+v0x556346c77aa0_0 .net "rst", 0 0, v0x556346c78090_0;  1 drivers
+v0x556346c77bb0_0 .net "updown", 0 0, v0x556346c78180_0;  1 drivers
+E_0x556346c631d0 .event posedge, v0x556346c51a80_0;
+S_0x556346c518a0 .scope begin, "COUNTER_4BIT_CYCLE" "COUNTER_4BIT_CYCLE" 3 29, 3 29 0, S_0x556346c65a50;
+ .timescale -9 -11;
+    .scope S_0x556346c65a50;
+T_0 ;
+    %wait E_0x556346c631d0;
+    %fork t_1, S_0x556346c518a0;
+    %jmp t_0;
+    .scope S_0x556346c518a0;
+t_1 ;
+    %load/vec4 v0x556346c77aa0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v0x556346c77920_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v0x556346c779e0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.2, 8;
+    %load/vec4 v0x556346c77840_0;
+    %assign/vec4 v0x556346c77920_0, 0;
+    %jmp T_0.3;
+T_0.2 ;
+    %load/vec4 v0x556346c77bb0_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.4, 8;
+    %load/vec4 v0x556346c77920_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v0x556346c77920_0, 0;
+    %jmp T_0.5;
+T_0.4 ;
+    %load/vec4 v0x556346c77920_0;
+    %subi 1, 0, 4;
+    %assign/vec4 v0x556346c77920_0, 0;
+T_0.5 ;
+T_0.3 ;
+T_0.1 ;
+    %end;
+    .scope S_0x556346c65a50;
+t_0 %join;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_0x556346c658c0;
+T_1 ;
+    %vpi_call 2 13 "$from_myhdl", v0x556346c77d30_0, v0x556346c78090_0, v0x556346c77df0_0, v0x556346c78180_0, v0x556346c77fc0_0 {0 0 0};
+    %vpi_call 2 20 "$to_myhdl", v0x556346c77ec0_0 {0 0 0};
+    %vpi_call 2 25 "$dumpfile", "tb_counter_4bit.lxt" {0 0 0};
+    %vpi_call 2 26 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x556346c658c0 {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "tb_counter_4bit.v";
+    "counter_4bit.v";