.gitmodules

@@ -1,3 +0,0 @@
-[submodule "7Segment_Lattice_ice40_UltraPlus"]
-	path = 7Segment_Lattice_ice40_UltraPlus
-	url = https://git.efi.th-nuernberg.de/gitea/schmidtsi76327/7Segment_Lattice_ice40_UltraPlus

.vscode/settings.json

@@ -1,3 +0,0 @@
-{
-    "python.pythonPath": "/usr/bin/python3"
-}

4-bit-counter-cocotb/.gitignore

@@ -1,15 +0,0 @@
-__pycache__/
-.vscode/
-
-tests/__pycache__/
-tests/sim_build/
-
-tests/results.xml
-tests/*.swp
-tests/*.vcd
-tests/*.lxt
-
-*.swp
-*.vcd
-*.lxt
-results.xml

4-bit-counter-cocotb/hdl/counter.v

@@ -1,29 +0,0 @@
-//////////////////////////////////////////////////////////////
-//  4-bit loadable up-down counter          //////
-//////////////////////////////////////////////////////////////
-
-module counter(clk, rst, data, updown, load, data_out);
-    
-    input clk, rst, load;
-    input updown;
-    input [3:0] data;
-
-    output reg [3:0] data_out;
-
-    always @(posedge clk)
-    begin
-        if(rst)
-            data_out <= 4'b0;
-        else if(load)
-            data_out <= data;
-        else
-            data_out <= ((updown)?(data_out + 1'b1):(data_out -1'b1));
-    end
-
-    // Dump waves
-    initial begin
-        $dumpfile("dump.vcd");
-        $dumpvars(1, counter);
-    end
-
-endmodule

4-bit-counter-cocotb/tests/Makefile

@@ -1,49 +0,0 @@
-###############################################################################
-# Copyright (c) 2013 Potential Ventures Ltd
-# Copyright (c) 2013 SolarFlare Communications Inc
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Potential Ventures Ltd,
-#       SolarFlare Communications Inc nor the
-#       names of its contributors may be used to endorse or promote products
-#       derived from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-###############################################################################
-
-TOPLEVEL_LANG ?= verilog
-
-PWD=$(shell pwd)
-
-ifeq ($(TOPLEVEL_LANG),verilog)
-    VERILOG_SOURCES = $(PWD)/../hdl/counter.v
-else ifeq ($(TOPLEVEL_LANG),vhdl)
-    VHDL_SOURCES = $(PWD)/../hdl/counter.vhdl
-else
-    $(error "A valid value (verilog or vhdl) was not provided for TOPLEVEL_LANG=$(TOPLEVEL_LANG)")
-endif
-
-TOPLEVEL := counter
-MODULE   := test_counter
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-
-clean::
-	rm -rf dump.vcd results.xml
-    

4-bit-counter-cocotb/tests/test_counter.py

@@ -1,98 +0,0 @@
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import Timer, RisingEdge, FallingEdge
-
-import random
-
-@cocotb.test()
-async def test_counter_reset(dut):
-    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
-    cocotb.fork(clock.start())              # Start the clock
-
-    await RisingEdge(dut.clk)
-    await RisingEdge(dut.clk)
-
-    dut.rst <= 1
-    await RisingEdge(dut.clk)
-    await FallingEdge(dut.clk)
-
-    cnt = dut.data_out.value.integer        # assert counter ouput is 0
-    assert cnt == 0
-    
-    await RisingEdge(dut.clk)
-    await RisingEdge(dut.clk)
-
-@cocotb.test()
-async def test_counter_load(dut):
-    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
-    cocotb.fork(clock.start())              # Start the clock
-
-    dut.rst <= 0
-    dut.load <= 1
-    soll = random.randint(0,15)
-    dut.data <= soll
-
-    await RisingEdge(dut.clk)
-    await FallingEdge(dut.clk)
-    assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
-
-
-
-@cocotb.test()
-async def test_counter_inc(dut):
-    """Test for count up"""
-
-    dut.rst <= 0
-    dut.load <= 0
-    dut.updown <= 1
-    dut.data <= random.randint(0,15)
-
-    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
-    cocotb.fork(clock.start())              # Start the clock
-
-    dut.rst <= 1
-    await RisingEdge(dut.clk)
-    await FallingEdge(dut.clk)
-    dut.rst <= 0
-
-    soll = 0
-    for _ in range(10):
-        assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
-
-        await RisingEdge(dut.clk)
-        soll += 1
-        await FallingEdge(dut.clk)
-
-
-@cocotb.test()
-async def test_counter_dec(dut):
-    """Test for count down"""
-
-    dut.rst <= 0
-    dut.load <= 0
-    dut.updown <= 0
-    dut.data <= 14
-    soll = 14
-
-    clock = Clock(dut.clk, 10, units="us")  # Create a 10us period clock on port clk
-    cocotb.fork(clock.start())              # Start the clock
-
-    dut.rst <= 1
-    await RisingEdge(dut.clk)
-    await FallingEdge(dut.clk)
-    dut.rst <= 0
-
-    dut.load <= 1
-    await RisingEdge(dut.clk)
-    await FallingEdge(dut.clk)
-    dut.load <= 0
-
-    for _ in range(10):
-        assert dut.data_out.value.integer == soll, f"counter value is incorrect: {dut.data_out.value.integer} != {soll}"
-
-        await RisingEdge(dut.clk)
-        soll -= 1
-        await FallingEdge(dut.clk)
-
-
-

4-bit-counter-myhdl/.gitignore

@@ -1,7 +0,0 @@
-__pycache__/
-.vscode/
-
-*.swp
-*.vcd
-*.lxt
-*.vvp

4-bit-counter-myhdl/counter_4bit.v

@@ -1,46 +0,0 @@
-// File: counter_4bit.v
-// Generated by MyHDL 0.11
-// Date: Mon Jun  7 19:39:23 2021
-
-
-`timescale 1ns/10ps
-
-module counter_4bit (
-    clk,
-    rst,
-    data,
-    updown,
-    load,
-    data_out
-);
-
-
-input clk;
-input rst;
-input [3:0] data;
-input updown;
-input load;
-output [3:0] data_out;
-reg [3:0] data_out;
-
-
-
-
-always @(posedge clk) begin: COUNTER_4BIT_CYCLE
-    if (rst) begin
-        data_out <= 0;
-    end
-    else if (load) begin
-        data_out <= data;
-    end
-    else begin
-        if (updown) begin
-            data_out <= (data_out + 1);
-        end
-        else begin
-            data_out <= (data_out - 1);
-        end
-    end
-end
-
-endmodule

4-bit-counter-myhdl/counter_4bit_conv.py

@@ -1,33 +0,0 @@
-import myhdl
-from myhdl import *
-
-@block
-def counter_4bit(clk, rst, data, updown, load, data_out):
-
-    @always(clk.posedge)
-    def cycle():
-        if rst:
-            data_out.next = 0
-        elif load:
-            data_out.next = data
-        else:
-            if updown:
-                data_out.next = data_out + 1
-            else:
-                data_out.next = data_out - 1
-
-    return cycle
-
-
-def convert():
-    clk = Signal(bool(0))
-    rst = Signal(bool(0)) # nur sync reset hier
-    # reset = ResetSignal(0, active=0, isasync=True)
-    updown = Signal(bool(0))
-    load = Signal(bool(0))
-    data = Signal(modbv(val=0, min=0, max=15)[4:])
-    data_out = Signal(modbv(val=0, min=0, max=15)[4:])
-
-    inst = counter_4bit(clk, rst, data, updown, load, data_out)
-    inst.convert(hdl='Verilog')
-    # inst.convert(hdl='VHDL')

4-bit-counter-myhdl/counter_4bit_tb.py

@@ -1,133 +0,0 @@
-import os
-import myhdl
-from myhdl import *
-
-
-module = 'counter_4bit'
-testbench = 'tb_%s' % module
-
-build_cmd = "iverilog -o %s.vvp %s.v %s.v" % (testbench, module, testbench)
-
-
-def tb_counter_4bit():
-    clk = Signal(bool(0))
-    rst = Signal(bool(0))
-    updown = Signal(bool(0))
-    load = Signal(bool(0))
-    data = Signal(modbv(val=0, min=0, max=15)[4:])
-    data_out = Signal(modbv(val=0, min=0, max=15)[4:])
-
-    # DUT
-    print(build_cmd)
-    if os.system(build_cmd):
-        raise Exception("Error running build command")
-
-    dut = Cosimulation(
-        "vvp -m myhdl %s.vvp -lxt2" % testbench,
-        clk=clk,
-        rst=rst,    
-        updown=updown,
-        load=load,
-        data=data,
-        data_out=data_out
-    )
-
-    @always(delay(4))
-    def clkgen():
-        clk.next = not clk
-
-    @instance
-    def check():
-        print("initialize")
-        clk.next = 0
-        rst.next = 0
-        load.next = 0
-        updown.next = 1
-        data.next = 0
-        
-        yield clk.posedge
-        yield clk.posedge
-
-        print("... OK")
-        print("test 1: reset")
-        yield clk.negedge
-        rst.next = 1
-        yield clk.posedge
-        yield clk.negedge
-        rst.next = 0
-        yield clk.posedge
-        
-        assert data_out == 0, f"assert failed with data_out {data_out} != 0"
-
-        yield clk.posedge
-        yield clk.posedge
-
-        
-        print("... OK")
-        print("test 2: load")
-
-        yield clk.posedge
-        load.next = 1
-        data.next = Signal(modbv(13)[4:])
-        yield clk.negedge
-        yield clk.posedge
-        yield clk.negedge
-        assert data_out == 13, f"assert failed with data_out {data_out} != {13}"
-
-        load.next = 0
-        yield clk.posedge
-        yield clk.negedge
-
-
-        print("... OK")
-        print("test 3: inc")
-
-        yield clk.negedge
-        rst.next = 1
-        yield clk.posedge
-        yield clk.negedge
-        rst.next = 0
-        soll = 0
-
-        for i in range(4):
-            assert data_out == soll, f"assert failed with data_out {int(data_out)} != {i}"
-
-            yield clk.posedge
-            soll += 1
-            yield clk.negedge
-
-        print("... OK")
-        print("test 4: dec")
-
-        soll = 13
-
-        yield clk.posedge
-        updown.next = 0
-        load.next = 1
-        data.next = Signal(modbv(soll)[4:])
-        yield clk.negedge
-        yield clk.posedge
-        yield clk.negedge
-        load.next = 0
-
-        for i in range(4):
-            assert data_out == soll, f"assert failed with data_out {int(data_out)} != {soll}"
-
-            yield clk.posedge
-            soll -= 1
-            yield clk.negedge
-
-
-        print("... OK")
-
-        for _ in range(10):
-            yield clk.posedge
-
-        raise StopSimulation
-
-    return instances()
-
-
-def simulate():
-    sim = Simulation(tb_counter_4bit())
-    sim.run()

4-bit-counter-myhdl/counter_reference.v

@@ -1,23 +0,0 @@
-//////////////////////////////////////////////////////////////
-//  4-bit loadable up-down counter          //////
-//////////////////////////////////////////////////////////////
-
-module counter(clk, rst, data, updown, load, data_out);
-
-    input clk, rst, load;
-    input updown;
-    input [3:0] data;
-
-    output reg [3:0] data_out;
-
-    always @(posedge clk)
-    begin
-        if(rst)
-            data_out <= 4'b0;
-        else if(load)
-            data_out <= data;
-        else
-            data_out <= ((updown)?(data_out + 1'b1):(data_out -1'b1));
-    end
-
-endmodule

4-bit-counter-myhdl/main.py

@@ -1,10 +0,0 @@
-import counter_4bit_conv, counter_4bit_tb
-import os
-
-# print("Konvertiere MyHDL Design in Verilog")
-# counter_4bit_conv.convert()
-
-print("Simuliere Verilog Design mit MyHDL")
-counter_4bit_tb.simulate()
-
-os.system("gtkwave.exe -S run.tcl *.lxt")

4-bit-counter-myhdl/run.tcl

@@ -1,22 +0,0 @@
-### --------------------------------------------------------------------
-### gtkwave.tcl
-### Author: Simon Schmidt
-### --------------------------------------------------------------------
-
-# Resources:
-# Manual: http://gtkwave.sourceforge.net/gtkwave.pdf#Appendix-E-Tcl-Command-Syntax
-
-# Add all signals
-set nfacs [ gtkwave::getNumFacs ]
-
-set all_facs [list]
-for {set i 0} {$i < $nfacs } {incr i} {
-    set facname [ gtkwave::getFacName $i ]
-    lappend all_facs "$facname"
-}
-
-set num_added [ gtkwave::addSignalsFromList $all_facs ]
-puts "num signals added: $num_added"
-
-# zoom full
-gtkwave::/Time/Zoom/Zoom_Full

4-bit-counter-myhdl/tb_counter_4bit.v

@@ -1,38 +0,0 @@
-module tb_counter_4bit;
-
-reg clk;
-reg rst;
-reg [3:0] data;
-reg updown;
-reg load;
-wire [3:0] data_out;
-
-
-
-initial begin
-    $from_myhdl(
-        clk,
-        rst,
-        data,
-        updown,
-        load
-    );
-    $to_myhdl(
-        data_out
-    );
-    
-    // dump file
-    $dumpfile("tb_counter_4bit.lxt");
-    $dumpvars(0, tb_counter_4bit);
-end
-
-counter_4bit dut(
-    clk,
-    rst,
-    data,
-    updown,
-    load,
-    data_out
-);
-
-endmodule

7Segment_Lattice_ice40_UltraPlus

@@ -1 +0,0 @@
-Subproject commit d567bd258c4e6cee6d2dc2866892824e890c5656

README.md

@@ -1,3 +1,3 @@
-# ESY1B Verifikation mit SystemVerilog und Python
+# ESY1B_SV_Python_Verifikation
 
 Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python" 

digitaler-filter-cocotb/.gitignore

@@ -1,8 +0,0 @@
-__pycache__/
-
-*.swp
-*.vcd
-*.lxt
-
-results.xml
-sim_build

digitaler-filter-cocotb/Makefile

@@ -1,12 +0,0 @@
-# cocotb setup
-MODULE = test
-TOPLEVEL = top
-VERILOG_SOURCES = top.v filter.v
-
-include $(shell cocotb-config --makefiles)/Makefile.sim
-
-# filters exported by pyfda always have module name set to top
-filter.v:
-	sed -i 's/top/filter/' $@
-
-.PHONY: filter.v

digitaler-filter-cocotb/filter.v

@@ -1,99 +0,0 @@
-/* Machine-generated using Migen */
-module filter(
-	input signed [15:0] i,
-	output signed [15:0] o,
-	input sys_clk,
-	input sys_rst
-);
-
-reg signed [15:0] sreg0 = 16'sd0;
-reg signed [15:0] sreg1 = 16'sd0;
-reg signed [15:0] sreg2 = 16'sd0;
-reg signed [15:0] sreg3 = 16'sd0;
-reg signed [15:0] sreg4 = 16'sd0;
-reg signed [15:0] sreg5 = 16'sd0;
-reg signed [15:0] sreg6 = 16'sd0;
-reg signed [15:0] sreg7 = 16'sd0;
-reg signed [15:0] sreg8 = 16'sd0;
-reg signed [15:0] sreg9 = 16'sd0;
-reg signed [15:0] sreg10 = 16'sd0;
-reg signed [15:0] sreg11 = 16'sd0;
-reg signed [15:0] sreg12 = 16'sd0;
-reg signed [15:0] sreg13 = 16'sd0;
-reg signed [15:0] sreg14 = 16'sd0;
-reg signed [15:0] sreg15 = 16'sd0;
-reg signed [15:0] sreg16 = 16'sd0;
-reg signed [15:0] sreg17 = 16'sd0;
-reg signed [15:0] sreg18 = 16'sd0;
-reg signed [15:0] sreg19 = 16'sd0;
-reg signed [15:0] sreg20 = 16'sd0;
-reg signed [35:0] sum_full = 36'sd0;
-wire signed [31:0] sum_accu;
-wire signed [35:0] sig_i_q0;
-wire signed [31:0] sig_o0;
-wire signed [31:0] sig_i_q1;
-wire signed [15:0] sig_o1;
-
-// synthesis translate_off
-reg dummy_s;
-initial dummy_s <= 1'd0;
-// synthesis translate_on
-
-assign sig_i_q0 = (sum_full <<< 1'd0);
-assign sig_o0 = sig_i_q0;
-assign sum_accu = sig_o0;
-assign sig_i_q1 = (sum_accu >>> 4'd15);
-assign sig_o1 = sig_i_q1;
-assign o = sig_o1;
-
-always @(posedge sys_clk) begin
-	sreg0 <= i;
-	sreg1 <= sreg0;
-	sreg2 <= sreg1;
-	sreg3 <= sreg2;
-	sreg4 <= sreg3;
-	sreg5 <= sreg4;
-	sreg6 <= sreg5;
-	sreg7 <= sreg6;
-	sreg8 <= sreg7;
-	sreg9 <= sreg8;
-	sreg10 <= sreg9;
-	sreg11 <= sreg10;
-	sreg12 <= sreg11;
-	sreg13 <= sreg12;
-	sreg14 <= sreg13;
-	sreg15 <= sreg14;
-	sreg16 <= sreg15;
-	sreg17 <= sreg16;
-	sreg18 <= sreg17;
-	sreg19 <= sreg18;
-	sreg20 <= sreg19;
-	sum_full <= ((((((((((((((((((((($signed({1'd0, 11'd1135}) * sreg0) + ($signed({1'd0, 10'd512}) * sreg1)) + ($signed({1'd0, 9'd364}) * sreg2)) + (6'sd46 * sreg3)) + (11'sd1406 * sreg4)) + (12'sd2625 * sreg5)) + (13'sd5777 * sreg6)) + (13'sd4839 * sreg7)) + (14'sd12231 * sreg8)) + (14'sd11695 * sreg9)) + ($signed({1'd0, 15'd27889}) * sreg10)) + (14'sd11695 * sreg11)) + (14'sd12231 * sreg12)) + (13'sd4839 * sreg13)) + (13'sd5777 * sreg14)) + (12'sd2625 * sreg15)) + (11'sd1406 * sreg16)) + (6'sd46 * sreg17)) + ($signed({1'd0, 9'd364}) * sreg18)) + ($signed({1'd0, 10'd512}) * sreg19)) + ($signed({1'd0, 11'd1135}) * sreg20));
-	if (sys_rst) begin
-		sreg0 <= 16'sd0;
-		sreg1 <= 16'sd0;
-		sreg2 <= 16'sd0;
-		sreg3 <= 16'sd0;
-		sreg4 <= 16'sd0;
-		sreg5 <= 16'sd0;
-		sreg6 <= 16'sd0;
-		sreg7 <= 16'sd0;
-		sreg8 <= 16'sd0;
-		sreg9 <= 16'sd0;
-		sreg10 <= 16'sd0;
-		sreg11 <= 16'sd0;
-		sreg12 <= 16'sd0;
-		sreg13 <= 16'sd0;
-		sreg14 <= 16'sd0;
-		sreg15 <= 16'sd0;
-		sreg16 <= 16'sd0;
-		sreg17 <= 16'sd0;
-		sreg18 <= 16'sd0;
-		sreg19 <= 16'sd0;
-		sreg20 <= 16'sd0;
-		sum_full <= 36'sd0;
-	end
-end
-
-endmodule
-

digitaler-filter-cocotb/test.py

@@ -1,32 +0,0 @@
-import cocotb
-from cocotb.clock import Clock
-from cocotb.triggers import RisingEdge
-
-import wave
-import struct
-import numpy as np
-
-@cocotb.test()
-async def test(dut):
-    clock = Clock(dut.clk, 10, units="us")
-    cocotb.fork(clock.start())
-
-    # open audio files for read and write
-    audio_in = wave.open('hello.wav')
-    audio_out = wave.open('out.wav', 'wb')
-    audio_out.setnchannels(audio_in.getnchannels())
-    audio_out.setsampwidth(audio_in.getsampwidth())
-    audio_out.setframerate(audio_in.getframerate())
-
-    nframes = audio_in.getnframes()
-    print("sending %d frames" % nframes)
-    
-    # process the audio through the dut
-    for i in range(nframes):
-        frame = audio_in.readframes(1)
-        val, = struct.unpack('h', frame)
-        dut.data_in <= val 
-        await RisingEdge(dut.clk)
-
-        raw_out = struct.pack('h', dut.data_out.value.signed_integer)
-        audio_out.writeframes(raw_out)

digitaler-filter-cocotb/test.sh

@@ -1,4 +0,0 @@
-#!/bin/bash
-make
-cp hello.wav out.wav /mnt/c/Users/simon/Google_Drive/OHM_BEI6_Simon/ESY1_KUNTZSCH/000_Studienarbeit/verilog/fftplot
-py.exe "C:\Users\simon\Google_Drive\OHM_BEI6_Simon\ESY1_KUNTZSCH\000_Studienarbeit\verilog\fftplot\fftplot.py"

digitaler-filter-cocotb/top.v

@@ -1,18 +0,0 @@
-`default_nettype none
-module top (
-    input wire clk,
-    input wire signed [15:0] data_in,
-    input wire signed [15:0] data_out
-    );
-
-    `ifdef COCOTB_SIM
-        initial begin
-            $dumpfile ("top.vcd");
-            $dumpvars (0, top);
-            #1;
-        end
-    `endif
-
-    filter filter (.i(data_in), .o(data_out), .sys_clk(clk), .sys_rst(1'b0));
-
-endmodule

digitaler-filter-cocotb/top_coco.gtkw

@@ -1,28 +0,0 @@
-[*]
-[*] GTKWave Analyzer v3.3.105 (w)1999-2020 BSI
-[*] Wed Sep 23 09:52:12 2020
-[*]
-[dumpfile] "/home/matt/work/fpga/pyfda-cocotb-demo/top.vcd"
-[dumpfile_mtime] "Wed Sep 23 09:51:27 2020"
-[dumpfile_size] 24963113
-[savefile] "/home/matt/work/fpga/pyfda-cocotb-demo/top_coco.gtkw"
-[timestart] 0
-[size] 2353 1179
-[pos] -1 -1
-*-36.000000 2010000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-[sst_width] 272
-[signals_width] 438
-[sst_expanded] 1
-[sst_vpaned_height] 349
-@28
-top.clk
-@8420
-top.data_in[15:0]
-@20000
--
-@8420
-top.data_out[15:0]
-@20000
--
-[pattern_trace] 1
-[pattern_trace] 0