ESY1A_B_Seminararbeiten/4-bit-counter-cocotb/tests/dump.vcd

$date
	Tue Jun  8 18:10:07 2021
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module counter $end
$var wire 1 ! clk $end
$var wire 4 " data [3:0] $end
$var wire 1 # load $end
$var wire 1 $ rst $end
$var wire 1 % updown $end
$var reg 4 & data_out [3:0] $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
bx &
z%
z$
z#
bz "
1!
$end
#5000000
0!
#10000000
1$
1!
#15000000
0!
#20000000
b0 &
1!
#25000000
0!
#30000000
1!
#35000000
0!
#40000000
1!
#40000001
0$
1#
b1110 "
#45000001
0!
#50000001
b1110 &
1!
#55000001
0!
#55000002
b0 &
1$
0#
1%
b1100 "
1!
#60000002
0$
0!
#65000002
b1 &
1!
#70000002
0!
#75000002
b10 &
1!
#80000002
0!
#85000002
b11 &
1!
#90000002
0!
#95000002
b100 &
1!
#100000002
0!
#105000002
b101 &
1!
#110000002
0!
#115000002
b110 &
1!
#120000002
0!
#125000002
b111 &
1!
#130000002
0!
#135000002
b1000 &
1!
#140000002
0!
#145000002
b1001 &
1!
#150000002
0!
#155000002
b1010 &
1!
#160000002
0!
#160000003
b0 &
1$
0%
b1110 "
1!
#165000003
0$
1#
0!
#170000003
b1110 &
1!
#175000003
0#
0!
#180000003
b1101 &
1!
#185000003
0!
#190000003
b1100 &
1!
#195000003
0!
#200000003
b1011 &
1!
#205000003
0!
#210000003
b1010 &
1!
#215000003
0!
#220000003
b1001 &
1!
#225000003
0!
#230000003
b1000 &
1!
#235000003
0!
#240000003
b111 &
1!
#245000003
0!
#250000003
b110 &
1!
#255000003
0!
#260000003
b101 &
1!
#265000003
0!
#270000003
b100 &
1!
#275000003
0!
#275000004