schmidtsi76327
/
ESY1A_B_Seminararbeiten
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
2 Commits
1 Branch
Tree: 2cd5d89e87
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from '2cd5d89e87'
${ noResults }
ESY1A_B_Seminararbeiten/.gitmodules

.gitmodules 181B
Raw Blame History

123 
  1. [submodule "7Segment_Lattice_ice40_UltraPlus"]

  2. 	path = 7Segment_Lattice_ice40_UltraPlus

  3. 	url = https://git.efi.th-nuernberg.de/gitea/schmidtsi76327/7Segment_Lattice_ice40_UltraPlus