Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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Simon Schmidt 2cd5d89e87 initial commit 3 years ago
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__pycache__ initial commit 3 years ago
sim_build initial commit 3 years ago
Makefile initial commit 3 years ago
dump.vcd initial commit 3 years ago
results.xml initial commit 3 years ago
test_counter.py initial commit 3 years ago