Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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top.v 379B

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  1. `default_nettype none
  2. module top (
  3. input wire clk,
  4. input wire signed [15:0] data_in,
  5. input wire signed [15:0] data_out
  6. );
  7. `ifdef COCOTB_SIM
  8. initial begin
  9. $dumpfile ("top.vcd");
  10. $dumpvars (0, top);
  11. #1;
  12. end
  13. `endif
  14. filter filter (.i(data_in), .o(data_out), .sys_clk(clk), .sys_rst(1'b0));
  15. endmodule