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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/4-bit-counter-myhdl
Simon Schmidt e71d8eb717 changed gitignore 3 years ago
..
.gitignore changed gitignore 3 years ago
counter_4bit.v initial commit 3 years ago
counter_4bit_conv.py initial commit 3 years ago
counter_4bit_tb.py initial commit 3 years ago
counter_reference.v initial commit 3 years ago
main.py initial commit 3 years ago
run.tcl initial commit 3 years ago
tb_counter_4bit.v initial commit 3 years ago