ESY1A_B_Seminararbeiten/7Segment_Lattice_ice40_UltraPlus/clocks.v

// generate clocks

module clocks
#(
   parameter PRE_PWM  = 28'd12,
   parameter PRE_7SEG = 28'd12,
   parameter PRE_COUNTER = 28'd12
)
(
   input clk, output clk_pwm, output clk_7seg, output clk_counter
);

   reg [27:0] counter = 28'd0;
   reg [27:0] counter_7seg = 28'd0;
   reg [27:0] counter_counter = 28'd0;
   reg clk_pwm;
   reg clk_7seg;
   reg clk_counter;

   always @(posedge clk)
   begin
      counter <= counter + 28'd1;
      if(counter >= (PRE_PWM-1))
         counter <= 28'd0;
      clk_pwm <= ( counter < PRE_PWM/2) ? 1'b1 : 1'b0;      
   end

   always @(posedge clk)
   begin
      counter_7seg <= counter_7seg + 28'd1;
      if(counter_7seg >= (PRE_7SEG-1))
         counter_7seg <= 28'd0;
      clk_7seg <= ( counter_7seg < PRE_7SEG/2) ? 1'b1 : 1'b0;      
   end
   
   always @(posedge clk)
   begin
      counter_counter <= counter_counter + 28'd1;
      if(counter_counter >= (PRE_COUNTER-1))
         counter_counter <= 28'd0;
      clk_counter <= ( counter_counter < PRE_COUNTER/2) ? 1'b1 : 1'b0;      
   end
endmodule