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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/7Segment_Lattice_ice40_Ultr.../io.pcf

io.pcf 655B
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  1. # For the iCE40 UltraPlus (iCE40UP5K-QFN) Breakout Board

  2. # 12 MHz Clock

  3. set_io clk 35

  4. 

  5. set_io LED_R 41

  6. set_io LED_G 40

  7. set_io LED_B 39

  8. set_io SW[0] 23

  9. set_io SW[1] 25

  10. set_io SW[2] 34

  11. set_io SW[3] 43

  12. 

  13. # bank 0,segments

  14. set_io seg_b 26 # IOT_39A

  15. set_io seg_a 27 # IOT_38B

  16. set_io seg_p 28 # IOT_41A

  17. set_io seg_f 31 # IOT_42B

  18. set_io seg_g 32 # IOT_43A

  19. set_io seg_e 37 # IOT_45A_G1

  20. set_io seg_d 42 # IOT_51A

  21. set_io seg_c 38 # IOT_50B

  22. # bank1 digit 

  23. set_io dig_1 21 # IOT_23B

  24. set_io dig_2 20 # IOT_25B_G3

  25. set_io dig_3 19 # IOT_29B

  26. set_io dig_4 18 # IOT_31B

  27. set_io dig_5 11 # IOT_20A

  28. 

  29. #spi

  30. set_io SPI_SS 16

  31. set_io SPI_SCK 15

  32. set_io SPI_MOSI 17

  33. set_io SPI_MISO 14