ESY1A_B_Seminararbeiten/i2c_slave_opencores/rtl/registerInterface.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
//// registerInterface.v                                          ////
////                                                              ////
//// This file is part of the i2cSlave opencores effort.
//// <http://www.opencores.org/cores//>                           ////
////                                                              ////
//// Module Description:                                          ////
//// You will need to modify this file to implement your 
//// interface.
//// Add your control and status bytes/bits to module inputs and outputs,
//// and also to the I2C read and write process blocks  
////                                                              ////
//// To Do:                                                       ////
//// 
////                                                              ////
//// Author(s):                                                   ////
//// - Steve Fielding, sfielding@base2designs.com                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Steve Fielding and OPENCORES.ORG          ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE. See the GNU Lesser General Public License for more  ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from <http://www.opencores.org/lgpl.shtml>                   ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
`include "i2cSlave_define.v"


module registerInterface (
  clk,
  addr,
  dataIn,
  writeEn,
  dataOut,
  tb_readEn,
  tb_writeEn,
  tb_addr,
  tb_dataIn,
  tb_dataOut
);

// i2c interface
input clk;
input [15:0] addr;
input [7:0] dataIn;
input writeEn;
output [7:0] dataOut;
reg [7:0] dataOut;

// speicher
reg [7:0] memory [16'hffff:0];

// tb interface
input tb_readEn;
input tb_writeEn;
input [15:0] tb_addr;
input [15:0] tb_dataIn;
output [15:0] tb_dataOut;
reg [15:0] tb_dataOut;

// --- TB Read
always @(posedge tb_readEn) begin
  tb_dataOut[15:8] <= memory[tb_addr];
  tb_dataOut[7:0] <= memory[tb_addr + 1'b1];
end

// --- TB Write
always @(posedge tb_writeEn) begin
  memory[tb_addr] <= tb_dataIn[15:8];
  memory[tb_addr + 1'b1] <= tb_dataIn[7:0];
end

// --- I2C Read
always @(posedge clk) begin
  dataOut <= memory[addr];
end

// --- I2C Write
always @(posedge clk) begin
  if (writeEn == 1'b1) begin
    memory[addr] <= dataIn;
  end
end

endmodule