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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/rtl/timescale.v

timescale.v 225B
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  1. //////////////////////////////////////////////////////////////////////

  2. // timescale.v                                              

  3. //////////////////////////////////////////////////////////////////////

  4. `timescale 1ns / 1ps