ESY1A_B_Seminararbeiten/i2c_slave_opencores/sim/filelist.icarus

../rtl/serialInterface.v
../rtl/registerInterface.v
../rtl/i2cSlave.v
../model/i2c_master_bit_ctrl.v
../model/i2c_master_byte_ctrl.v
../model/i2c_master_top.v
../model/wb_master_model.v
../bench/multiByteReadWrite.v
../bench/testHarness.v
../bench/testCase0.v

+incdir+../rtl
+incdir+../bench
+incdir+../model
+define+SIM_COMPILE