schmidtsi76327
/
ESY1A_B_Seminararbeiten
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
10 Commits
1 Branch
Tree: b3637d6d76
Branches Tags
${ item.name }
Create branch ${ searchTerm }
from 'b3637d6d76'
${ noResults }
ESY1A_B_Seminararbeiten/i2c_slave_opencores/sim/gtkwave.ini

gtkwave.ini 725B
Raw Blame History

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950 
  1. #

  2. # sample rc file

  3. #

  4. hier_max_level 1

  5. force_toolbars 0

  6. 

  7. dynamic_resizing 1

  8. hpane_pack 1

  9. use_vcd 0

  10. #initial_window_x 700

  11. #initial_window_y 400

  12. use_maxtime_display 0

  13. 

  14. enable_vcd_autosave 0

  15. use_roundcaps 1

  16. 

  17. use_nonprop_fonts yes

  18. enable_horiz_grid yes

  19. use_big_fonts no

  20. constant_marker_update yes

  21. show_grid yes

  22. show_base_symbols no

  23. use_roundcaps yes

  24. 

  25. atomic_vectors yes

  26. vcd_explicit_zero_subscripts no

  27. 

  28. #

  29. # color additions

  30. #

  31. color_back   000000

  32. color_grid   202070

  33. color_high   00ff00

  34. color_low    008000

  35. color_trans  00c000

  36. color_mid    c0c000

  37. 

  38. color_value  ffffff

  39. color_vbox   00ff00

  40. color_vtrans 00c000

  41. 

  42. color_x      00ff00

  43. color_xfill  004000

  44. 

  45. color_umark  ff8080

  46. color_mark   ffff80

  47. 

  48. color_time   ffffff

  49. color_timeb  000000