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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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${ item.name }
Create branch ${ searchTerm }
from 'b3637d6d76'
${ noResults }
ESY1A_B_Seminararbeiten/i2c_slave_opencores/sim/myWave.sav

myWave.sav 344B
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  3. testHarness.u_i2cSlave.scl

  4. testHarness.u_i2cSlave.sda

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  6. testHarness.u_i2cSlave.tb_readEn

  7. testHarness.u_i2cSlave.tb_writeEn

  8. testHarness.u_i2cSlave.tb_addr[15:0]

  9. testHarness.u_i2cSlave.tb_dataIn[15:0]

  10. testHarness.u_i2cSlave.tb_dataOut[15:0]