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ESY1A_B_Seminararbeiten
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Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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ESY1A_B_Seminararbeiten/i2c_slave_opencores/sim/simulate.sh

simulate.sh 71B
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12 
  1. #!/bin/sh

  2. iverilog -o testHarness -cfilelist.icarus && vvp testHarness