Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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counter_rd_mon.sv 709B

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  1. class counter_rd_mon;
  2. virtual counter_if.RD_MON rdmon_if;
  3. mailbox #(counter_trans) rdmon2sb;
  4. counter_trans trans_h;
  5. counter_trans rd2sb_h;
  6. function new( virtual counter_if.RD_MON rdmon_if,
  7. mailbox #(counter_trans) rdmon2sb);
  8. this.rdmon_if = rdmon_if;
  9. this.rdmon2sb = rdmon2sb;
  10. trans_h = new;
  11. endfunction
  12. task monitor();
  13. @(rdmon_if.rdmon_cb)
  14. trans_h.data_out = rdmon_if.rdmon_cb.data_out;
  15. if($isunknown(rdmon_if.rdmon_cb.data_out))
  16. trans_h.data_out = 0;
  17. endtask
  18. task start();
  19. fork
  20. forever
  21. begin
  22. monitor();
  23. trans_h.display("DATA FROM READ MONITOR");
  24. rd2sb_h = new trans_h;
  25. rdmon2sb.put(rd2sb_h);
  26. end
  27. join_none
  28. endtask
  29. endclass: counter_rd_mon