Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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counter_trans.sv 970B

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  1. class counter_trans;
  2. rand bit [3:0] data;
  3. rand bit rst;
  4. rand bit load;
  5. rand bit updown;
  6. bit [3:0] data_out;
  7. static int trans_id;
  8. //Constraints to control frequency of reset and load
  9. constraint r1{rst dist {0:=50, 1:=1};}
  10. constraint l1{load dist {0:=20, 1:=1};}
  11. function void post_randomize();
  12. this.display("RANDOMIZED DATA");
  13. endfunction
  14. function void display(string message);
  15. $display("-------------------------------------------------");
  16. $display("%s",message);
  17. $display("\tTransaction ID: %d", trans_id);
  18. $display("\tRESET = %d\n\tLOAD = %d\n\tUP-DOWN = %d\n\tDATA = %d", rst, load, updown, data);
  19. $display("-------------------------------------------------");
  20. endfunction
  21. function bit compare(counter_trans rcvd);
  22. compare = 1'b1;
  23. if(this.data_out != rcvd.data_out)
  24. begin
  25. compare = 1'b0;
  26. $display("DATA MISMATCH");
  27. $display(this.data_out, " != ", rcvd.data_out);
  28. $stop;
  29. end
  30. endfunction
  31. endclass: counter_trans