Verwendeter Programmcode in Studienarbeit für ESY1B zum Thema "Verifikation mit SystemVerilog und Python"
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counter.v 682B

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  1. //////////////////////////////////////////////////////////////
  2. // 4-bit loadable up-down counter //////
  3. //////////////////////////////////////////////////////////////
  4. module counter(clk, rst, data, updown, load, data_out);
  5. input clk, rst, load;
  6. input updown;
  7. input [3:0] data;
  8. output reg [3:0] data_out;
  9. always @(posedge clk)
  10. begin
  11. if(rst)
  12. data_out <= 4'b0;
  13. else if(load)
  14. data_out <= data;
  15. else
  16. data_out <= ((updown)?(data_out + 1'b1):(data_out -1'b1));
  17. end
  18. // Dump waves
  19. initial begin
  20. $dumpfile("dump.vcd");
  21. $dumpvars(1, counter);
  22. end
  23. endmodule