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zieglerhe c90753aa23 New FFT.vhd Template and Fix FFT TB (expected values)
2025-05-30 11:33:35 +02:00
hardware
New FFT.vhd Template and Fix FFT TB (expected values)
2025-05-30 11:33:35 +02:00
software/signal_processing
Initial commit
2023-10-31 07:47:27 +01:00
tests
New FFT.vhd Template and Fix FFT TB (expected values)
2025-05-30 11:33:35 +02:00
.gitignore
Initial commit
2023-10-31 07:47:27 +01:00
data_channel_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_task_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hardware_timestamp_hw.tcl
Initial commit
2023-10-31 07:47:27 +01:00
hdl_sources.qsf
Initial commit
2023-10-31 07:47:27 +01:00
init.sh
Initial commit
2023-10-31 07:47:27 +01:00
Makefile
Initial commit
2023-10-31 07:47:27 +01:00
niosII.qsys
Initial commit
2023-10-31 07:47:27 +01:00
signal_processing.cdf
Initial commit
2023-10-31 07:47:27 +01:00
signal_processing.qpf
Initial commit
2023-10-31 07:47:27 +01:00
signal_processing.qsf
Initial commit
2023-10-31 07:47:27 +01:00
Description
Lösung des Praktikums Systementwurf
259 KiB
Languages
VHDL 36.8%
C 17.5%
Verilog 15%
Python 10.7%
Makefile 8.2%
Other 11.7%