schoeffelbe82781/signal_processing_vorlage
1
0
Fork 0
forked from KutningJo/signal_processing_vorlage
Code Issues Pull Requests Releases Wiki Activity

Added Rand Software, started Rand Hardware, Fixed error in Task

Browse Source
This commit is contained in:
schoeffelbe82781
2024-11-27 11:28:35 +01:00
parent c7ee1a4da7
commit 4cb356e25b
4 changed files with 116 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
hardware/signal_processing/.sine.vhd.swo
BIN
View File
Binary file not shown.
hardware/signal_processing/rand.vhd
+50 -3
View File
@@ -26,6 +26,19 @@ architecture rtl of rand is
signal next_task_state : work.task.State;
signal index : integer range 0 to work.task.STREAM_LEN;
type CalcState is (
CALC_IDLE,
CALC_WRITE
);
signal Calc_State : CalcState;
signal lsfr : SIGNED( 31 downto 0 );
signal lsfr_std_logic : std_logic_vector( 31 downto 0 );
signal POLYNOM : std_logic_vector (31 downto 0);
signal lsfr_dump : SIGNED( 31 downto 0 );
begin
task_state_transitions : process ( current_task_state, task_start, index ) is
begin
@@ -50,17 +63,50 @@ begin
begin
if ( reset = '1' ) then
current_task_state <= work.task.TASK_IDLE;
Calc_State <= CALC_IDLE;
lsfr <= SIGNED(seed);
lsfr_std_logic <= seed;
POLYNOM <= (others => '0');
POLYNOM(31) <= '1';
POLYNOM(21) <= '1';
POLYNOM(1) <= '1';
POLYNOM(0) <= '1';
index <= 0;
elsif ( rising_edge( clk ) ) then
current_task_state <= next_task_state;
case next_task_state is
when work.task.TASK_IDLE =>
index <= 0;
lsfr <= SIGNED(seed);
signal_write <= '0';
when work.task.TASK_RUNNING =>
index <= index + 1;
signal_write <= '1';
signal_writedata <= ( others => '0' );
case Calc_State is
when CALC_IDLE =>
signal_write <= '0';
lsfr_std_logic <= STD_LOGIC_VECTOR(lsfr);
if(lsfr_std_logic(0) = '1') then
lsfr <= SIGNED(lsfr_std_logic srl 1);
lsfr <= SIGNED(lsfr_std_logic XOR POLYNOM);
else
lsfr <= SIGNED(lsfr_std_logic srl 1);
end if;
lsfr <= SIGNED(lsfr_std_logic);
lsfr_dump <= lsfr;
if(lsfr_std_logic(30) = '1') then
lsfr <= lsfr(31 downto 31) & "1000000" & lsfr(23 downto 0);
else
lsfr <= lsfr(31 downto 31) & "011111" & lsfr(24 downto 0);
end if;
Calc_State <= CALC_WRITE;
when CALC_WRITE =>
signal_write <= '1';
index <= index + 1;
Calc_State <= CALC_IDLE;
end case;
when work.task.TASK_DONE =>
index <= 0;
signal_write <= '0';
@@ -69,5 +115,6 @@ begin
end process sync;
task_state <= current_task_state;
signal_writedata <= STD_LOGIC_VECTOR(lsfr);
end architecture rtl;