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signal next_task_state : work.task.State; |
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signal next_task_state : work.task.State; |
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signal index : integer range 0 to work.task.STREAM_LEN; |
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signal index : integer range 0 to work.task.STREAM_LEN; |
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type CalcState is ( |
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CALC_IDLE, |
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CALC_WRITE |
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); |
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signal Calc_State : CalcState; |
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signal lsfr : SIGNED( 31 downto 0 ); |
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signal lsfr_std_logic : std_logic_vector( 31 downto 0 ); |
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signal POLYNOM : std_logic_vector (31 downto 0); |
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signal lsfr_dump : SIGNED( 31 downto 0 ); |
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begin |
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begin |
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task_state_transitions : process ( current_task_state, task_start, index ) is |
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task_state_transitions : process ( current_task_state, task_start, index ) is |
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begin |
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begin |
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begin |
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begin |
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if ( reset = '1' ) then |
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if ( reset = '1' ) then |
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current_task_state <= work.task.TASK_IDLE; |
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current_task_state <= work.task.TASK_IDLE; |
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Calc_State <= CALC_IDLE; |
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lsfr <= SIGNED(seed); |
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lsfr_std_logic <= seed; |
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POLYNOM <= (others => '0'); |
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POLYNOM(31) <= '1'; |
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POLYNOM(21) <= '1'; |
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POLYNOM(1) <= '1'; |
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POLYNOM(0) <= '1'; |
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index <= 0; |
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index <= 0; |
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elsif ( rising_edge( clk ) ) then |
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elsif ( rising_edge( clk ) ) then |
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current_task_state <= next_task_state; |
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current_task_state <= next_task_state; |
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case next_task_state is |
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case next_task_state is |
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when work.task.TASK_IDLE => |
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when work.task.TASK_IDLE => |
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index <= 0; |
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index <= 0; |
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lsfr <= SIGNED(seed); |
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signal_write <= '0'; |
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signal_write <= '0'; |
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when work.task.TASK_RUNNING => |
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when work.task.TASK_RUNNING => |
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index <= index + 1; |
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signal_write <= '1'; |
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signal_writedata <= ( others => '0' ); |
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case Calc_State is |
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when CALC_IDLE => |
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signal_write <= '0'; |
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lsfr_std_logic <= STD_LOGIC_VECTOR(lsfr); |
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if(lsfr_std_logic(0) = '1') then |
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lsfr <= SIGNED(lsfr_std_logic srl 1); |
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lsfr <= SIGNED(lsfr_std_logic XOR POLYNOM); |
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else |
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lsfr <= SIGNED(lsfr_std_logic srl 1); |
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end if; |
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lsfr <= SIGNED(lsfr_std_logic); |
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lsfr_dump <= lsfr; |
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if(lsfr_std_logic(30) = '1') then |
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lsfr <= lsfr(31 downto 31) & "1000000" & lsfr(23 downto 0); |
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else |
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lsfr <= lsfr(31 downto 31) & "011111" & lsfr(24 downto 0); |
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end if; |
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Calc_State <= CALC_WRITE; |
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when CALC_WRITE => |
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signal_write <= '1'; |
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index <= index + 1; |
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Calc_State <= CALC_IDLE; |
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end case; |
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when work.task.TASK_DONE => |
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when work.task.TASK_DONE => |
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index <= 0; |
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index <= 0; |
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signal_write <= '0'; |
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signal_write <= '0'; |
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end process sync; |
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end process sync; |
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task_state <= current_task_state; |
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task_state <= current_task_state; |
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signal_writedata <= STD_LOGIC_VECTOR(lsfr); |
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end architecture rtl; |
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end architecture rtl; |