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signal_processing_vorlage
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Loesung des Praktikums Systementwurf - Bjarne Hoesch - Bernhard Schoeffel
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signal_processing_vorlage/hardware/signal_processing
schoeffelbe82781 a980ef180e Finished Task Rand in vhdl 2 weeks ago
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.sine.vhd.swo Added Rand Software, started Rand Hardware, Fixed error in Task 3 weeks ago
add.vhd Implemented Task Add in c an vhdl. Still testing 1 month ago
crc.vhd Initial commit 1 year ago
fft.vhd Initial commit 1 year ago
rand.vhd Finished Task Rand in vhdl 2 weeks ago
signal_processing.vhd Initial commit 1 year ago
sine.vhd Finished VHDL for Sine Task 1 month ago