schoeffelbe82781/signal_processing_vorlage
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a980ef180eae87ead69c6dd216556f7b34953caf
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6 Commits
Author SHA1 Message Date
schoeffelbe82781 a980ef180e Finished Task Rand in vhdl 2024-12-04 09:37:28 +01:00
schoeffelbe82781 4cb356e25b Added Rand Software, started Rand Hardware, Fixed error in Task 2024-11-27 11:28:35 +01:00
schoeffelbe82781 c7ee1a4da7 Finished VHDL for Sine Task 2024-11-20 10:02:38 +01:00
schoeffelbe82781 151772a809 Started implementing Task Sine in vhdl 2024-11-13 11:08:56 +01:00
schoeffelbe82781 344619c957 Implemented Task Add in c an vhdl. Still testing 2024-11-13 09:58:47 +01:00
Johannes Kutning 0d1b73e3e0 Initial commit 2023-10-31 07:47:27 +01:00