solmazal74684 1c6c6a26d9 rand angepasst

2025-11-25 10:15:33 +01:00

hardware

rand angepasst

2025-11-25 10:15:33 +01:00

software/signal_processing

Initial commit

2023-10-31 07:47:27 +01:00

tests

New FFT.vhd Template and Fix FFT TB (expected values)

2025-05-30 11:33:35 +02:00

.gitignore

Initial commit

2023-10-31 07:47:27 +01:00

data_channel_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_task_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hardware_timestamp_hw.tcl

Initial commit

2023-10-31 07:47:27 +01:00

hdl_sources.qsf

Initial commit

2023-10-31 07:47:27 +01:00

init.sh

Initial commit

2023-10-31 07:47:27 +01:00

Makefile

Initial commit

2023-10-31 07:47:27 +01:00

niosII.qsys

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.cdf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qpf

Initial commit

2023-10-31 07:47:27 +01:00

signal_processing.qsf

Initial commit

2023-10-31 07:47:27 +01:00

Description

Lösung des Praktikums Systementwurf

19 MiB

Languages

VHDL 37.5%

C 17.1%

Verilog 14.9%

Python 10.6%

Makefile 8.2%

Other 11.6%