116 lines
6.1 KiB
Plaintext
116 lines
6.1 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2021.2 (64-bit)
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# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
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# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
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# Start of session at: Wed Mar 16 18:29:30 2022
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# Process ID: 1824
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# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test
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# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr
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# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log
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# Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou
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# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
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#-----------------------------------------------------------
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start_gui
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open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr
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create_bd_design "IO_Test"
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update_compile_order -fileset sources_1
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}
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file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new
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close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]
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add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
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update_compile_order -fileset sources_1
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close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]
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add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd
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update_compile_order -fileset sources_1
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export_ip_user_files -of_objects [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet
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remove_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v
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update_compile_order -fileset sources_1
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update_compile_order -fileset sources_1
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update_compile_order -fileset sources_1
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update_compile_order -fileset sources_1
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launch_runs synth_1 -jobs 6
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wait_on_run synth_1
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launch_simulation
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reset_run synth_1
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launch_runs synth_1 -jobs 6
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wait_on_run synth_1
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launch_simulation
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source pwm_test.tcl
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launch_runs impl_1 -jobs 6
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wait_on_run impl_1
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open_run impl_1
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export_ip_user_files -of_objects [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet
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remove_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd
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file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]
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add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
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update_compile_order -fileset sim_1
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update_compile_order -fileset sim_1
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reset_run synth_1
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launch_runs synth_1 -jobs 6
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wait_on_run synth_1
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launch_runs impl_1 -jobs 6
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wait_on_run impl_1
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refresh_design
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launch_simulation
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launch_simulation
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launch_simulation
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reset_run synth_1
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launch_runs synth_1 -jobs 6
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wait_on_run synth_1
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launch_simulation
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launch_simulation -mode post-synthesis -type functional
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source pwm_test_db.tcl
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relaunch_sim
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relaunch_sim
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }}
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relaunch_sim
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }}
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launch_simulation
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relaunch_sim
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relaunch_sim
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }}
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relaunch_sim
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }}
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }}
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relaunch_sim
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current_wave_config {Untitled 2}
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add_wave {{/pwm_test_db/uut}}
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relaunch_sim
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save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
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add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
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set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]
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set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]
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relaunch_sim
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relaunch_sim
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launch_simulation
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relaunch_sim
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reset_run synth_1
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launch_runs synth_1 -jobs 6
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wait_on_run synth_1
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relaunch_sim
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relaunch_sim
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reset_simulation -simset sim_1 -mode behavioral
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relaunch_sim
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reset_simulation -simset sim_1 -mode post-synthesis -type timing
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close_design
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launch_simulation -mode post-synthesis -type timing
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open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg
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source pwm_test_db.tcl
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save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}
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close_sim
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current_sim simulation_2
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close_sim
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close_sim
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