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FPGA Projektarbeit
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FPGA_Projekt/Coraz7_Test/vivado_1824.backup.jou

vivado_1824.backup.jou 6.1KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Wed Mar 16 18:29:30 2022

  6. # Process ID: 1824

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr

  15. create_bd_design "IO_Test"

  16. update_compile_order -fileset sources_1

  17. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  18. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  19. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  20. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  21. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  22. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  23. file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new

  24. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]

  25. add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v

  26. update_compile_order -fileset sources_1

  27. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]

  28. add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd

  29. update_compile_order -fileset sources_1

  30. export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet

  31. remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v

  32. update_compile_order -fileset sources_1

  33. update_compile_order -fileset sources_1

  34. update_compile_order -fileset sources_1

  35. update_compile_order -fileset sources_1

  36. launch_runs synth_1 -jobs 6

  37. wait_on_run synth_1

  38. launch_simulation

  39. reset_run synth_1

  40. launch_runs synth_1 -jobs 6

  41. wait_on_run synth_1

  42. launch_simulation

  43. source pwm_test.tcl

  44. launch_runs impl_1 -jobs 6

  45. wait_on_run impl_1

  46. open_run impl_1

  47. export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet

  48. remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd

  49. file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new

  50. set_property SOURCE_SET sources_1 [get_filesets sim_1]

  51. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]

  52. add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd

  53. update_compile_order -fileset sim_1

  54. update_compile_order -fileset sim_1

  55. reset_run synth_1

  56. launch_runs synth_1 -jobs 6

  57. wait_on_run synth_1

  58. launch_runs impl_1 -jobs 6

  59. wait_on_run impl_1

  60. refresh_design

  61. launch_simulation

  62. launch_simulation

  63. launch_simulation

  64. reset_run synth_1

  65. launch_runs synth_1 -jobs 6

  66. wait_on_run synth_1

  67. launch_simulation

  68. launch_simulation -mode post-synthesis -type functional

  69. source pwm_test_db.tcl

  70. relaunch_sim

  71. relaunch_sim

  72. current_wave_config {Untitled 2}

  73. add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 

  74. relaunch_sim

  75. current_wave_config {Untitled 2}

  76. add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 

  77. launch_simulation

  78. relaunch_sim

  79. relaunch_sim

  80. current_wave_config {Untitled 2}

  81. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} 

  82. relaunch_sim

  83. current_wave_config {Untitled 2}

  84. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} 

  85. current_wave_config {Untitled 2}

  86. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} 

  87. relaunch_sim

  88. current_wave_config {Untitled 2}

  89. add_wave {{/pwm_test_db/uut}} 

  90. relaunch_sim

  91. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}

  92. add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg

  93. set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]

  94. set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]

  95. relaunch_sim

  96. relaunch_sim

  97. launch_simulation

  98. relaunch_sim

  99. reset_run synth_1

  100. launch_runs synth_1 -jobs 6

  101. wait_on_run synth_1

  102. relaunch_sim

  103. relaunch_sim

  104. reset_simulation -simset sim_1 -mode behavioral

  105. relaunch_sim

  106. reset_simulation -simset sim_1 -mode post-synthesis -type timing

  107. close_design

  108. launch_simulation -mode post-synthesis -type timing

  109. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg

  110. source pwm_test_db.tcl

  111. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}

  112. close_sim

  113. current_sim simulation_2

  114. close_sim

  115. close_sim