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FPGA Projektarbeit
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FPGA_Projekt/Coraz7_Test/vivado_1824.backup.log

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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Wed Mar 16 18:29:30 2022

  6. # Process ID: 1824

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent21192 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.xpr

  15. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  16. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  17. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  18. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  19. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  20. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available

  21. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available

  22. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available

  23. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  24. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  25. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  26. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  27. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available

  28. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  29. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  30. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  31. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available

  32. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available

  33. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available

  34. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available

  35. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available

  36. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  37. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  38. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available

  39. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available

  40. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  41. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  42. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  43. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  44. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  45. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  46. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  47. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available

  48. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  49. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  50. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  51. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available

  52. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available

  53. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  54. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  55. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  56. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  57. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  58. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available

  59. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available

  60. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1'.

  61. Scanning sources...

  62. Finished scanning sources

  63. INFO: [IP_Flow 19-234] Refreshing IP repositories

  64. INFO: [IP_Flow 19-1704] No user IP repositories specified

  65. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.

  66. open_project: Time (s): cpu = 00:00:20 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000

  67. create_bd_design "IO_Test"

  68. Wrote  : <C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Coraz7_Test\Coraz7_Test.srcs\sources_1\bd\IO_Test\IO_Test.bd> 

  69. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.gen/sources_1/bd/IO_Test for IO_Test cannot be found.

  70. create_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1252.246 ; gain = 0.000

  71. update_compile_order -fileset sources_1

  72. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  73. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  74. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  75. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  76. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  77. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd}

  78. file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new

  79. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v w ]

  80. add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v

  81. update_compile_order -fileset sources_1

  82. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd w ]

  83. add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd

  84. update_compile_order -fileset sources_1

  85. export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v] -no_script -reset -force -quiet

  86. remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/IO_Test.v

  87. update_compile_order -fileset sources_1

  88. update_compile_order -fileset sources_1

  89. update_compile_order -fileset sources_1

  90. update_compile_order -fileset sources_1

  91. launch_runs synth_1 -jobs 6

  92. WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.

  93. [Wed Mar 16 19:55:26 2022] Launched synth_1...

  94. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  95. launch_simulation

  96. Command: launch_simulation 

  97. INFO: [Vivado 12-12493] Simulation top is 'pwm_test'

  98. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  99. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  100. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  101. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  102. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  103. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  104. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'...

  105. INFO: [USF-XSim-97] Finding global include files...

  106. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  107. INFO: [USF-XSim-2] XSim::Compile design

  108. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  109. "xvhdl --incr --relax -prj pwm_test_vhdl.prj"

  110. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  111. INFO: [VRFC 10-3107] analyzing entity 'pwm_test'

  112. ERROR: [VRFC 10-3031] 'led' with mode 'out' cannot be read [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]

  113. ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:39]

  114. INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' ignored due to errors

  115. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  116. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'

  117. ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.

  118. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  119. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  120. reset_run synth_1

  121. launch_runs synth_1 -jobs 6

  122. WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.

  123. [Wed Mar 16 19:57:51 2022] Launched synth_1...

  124. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  125. launch_simulation

  126. Command: launch_simulation 

  127. INFO: [Vivado 12-12493] Simulation top is 'pwm_test'

  128. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  129. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  130. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  131. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  132. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  133. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  134. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test' in fileset 'sim_1'...

  135. INFO: [USF-XSim-97] Finding global include files...

  136. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  137. INFO: [USF-XSim-2] XSim::Compile design

  138. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  139. "xvhdl --incr --relax -prj pwm_test_vhdl.prj"

  140. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  141. INFO: [VRFC 10-3107] analyzing entity 'pwm_test'

  142. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  143. INFO: [USF-XSim-3] XSim::Elaborate design

  144. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  145. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log"

  146. Vivado Simulator v2021.2

  147. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  148. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_behav xil_defaultlib.pwm_test -log elaborate.log 

  149. Using 2 slave threads.

  150. Starting static elaboration

  151. Completed static elaboration

  152. Starting simulation data flow analysis

  153. Completed simulation data flow analysis

  154. Time Resolution for simulation is 1ps

  155. Compiling package std.standard

  156. Compiling package std.textio

  157. Compiling package ieee.std_logic_1164

  158. Compiling architecture behavioral of entity xil_defaultlib.pwm_test

  159. Built simulation snapshot pwm_test_behav

  160. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  161. INFO: [USF-XSim-4] XSim::Simulate design

  162. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim'

  163. INFO: [USF-XSim-98] *** Running xsim

  164.    with args "pwm_test_behav -key {Behavioral:sim_1:Functional:pwm_test} -tclbatch {pwm_test.tcl} -log {simulate.log}"

  165. INFO: [USF-XSim-8] Loading simulator feature

  166. Time resolution is 1 ps

  167. source pwm_test.tcl

  168. # set curr_wave [current_wave_config]

  169. # if { [string length $curr_wave] == 0 } {

  170. #   if { [llength [get_objects]] > 0} {

  171. #     add_wave /

  172. #     set_property needs_save false [current_wave_config]

  173. #   } else {

  174. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  175. #   }

  176. # }

  177. # run 1000ns

  178. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_behav' loaded.

  179. INFO: [USF-XSim-97] XSim simulation ran for 1000ns

  180. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1349.082 ; gain = 26.551

  181. launch_runs impl_1 -jobs 6

  182. [Wed Mar 16 19:58:36 2022] Launched impl_1...

  183. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log

  184. open_run impl_1

  185. INFO: [Device 21-403] Loading part xc7z010clg400-1

  186. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1688.973 ; gain = 0.000

  187. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  188. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  189. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  190. INFO: [Project 1-570] Preparing netlist for logic optimization

  191. Reading XDEF placement.

  192. Reading placer database...

  193. Reading XDEF routing.

  194. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1764.523 ; gain = 0.172

  195. Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |

  196. Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.046 . Memory (MB): peak = 1764.523 ; gain = 0.172

  197. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.715 ; gain = 0.000

  198. INFO: [Project 1-111] Unisim Transformation Summary:

  199. No Unisim elements were transformed.

  200. 

  201. open_run: Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2238.512 ; gain = 881.695

  202. WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.

  203. export_ip_user_files -of_objects  [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd] -no_script -reset -force -quiet

  204. remove_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/IO_Test.bd

  205. Wrote  : <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sources_1/bd/IO_Test/ui/bd_316ac62b.ui> 

  206. file mkdir C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new

  207. set_property SOURCE_SET sources_1 [get_filesets sim_1]

  208. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd w ]

  209. add_files -fileset sim_1 C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd

  210. update_compile_order -fileset sim_1

  211. update_compile_order -fileset sim_1

  212. reset_run synth_1

  213. INFO: [Project 1-1160] Copying file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp to C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1 and adding it to utils fileset

  214. launch_runs synth_1 -jobs 6

  215. [Wed Mar 16 20:13:13 2022] Launched synth_1...

  216. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  217. launch_runs impl_1 -jobs 6

  218. [Wed Mar 16 20:13:57 2022] Launched impl_1...

  219. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/impl_1/runme.log

  220. refresh_design

  221. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2357.781 ; gain = 0.000

  222. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  223. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  224. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  225. INFO: [Project 1-570] Preparing netlist for logic optimization

  226. Reading XDEF placement.

  227. Reading placer database...

  228. Reading XDEF routing.

  229. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.054 . Memory (MB): peak = 2357.781 ; gain = 0.000

  230. Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB |

  231. Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.055 . Memory (MB): peak = 2357.781 ; gain = 0.000

  232. WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.

  233. launch_simulation

  234. Command: launch_simulation 

  235. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  236. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  237. launch_simulation

  238. Command: launch_simulation 

  239. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  240. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  241. launch_simulation

  242. Command: launch_simulation 

  243. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  244. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  245. reset_run synth_1

  246. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp

  247. launch_runs synth_1 -jobs 6

  248. [Wed Mar 16 20:16:57 2022] Launched synth_1...

  249. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  250. launch_simulation

  251. Command: launch_simulation 

  252. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  253. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  254. launch_simulation -mode post-synthesis -type functional

  255. Command: launch_simulation  -mode post-synthesis -type functional

  256. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  257. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  258. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  259. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  260. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  261. Design is defaulting to impl run constrset: constrs_1

  262. Design is defaulting to synth run part: xc7z010clg400-1

  263. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2379.422 ; gain = 0.000

  264. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  265. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  266. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  267. INFO: [Project 1-570] Preparing netlist for logic optimization

  268. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  269. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2431.441 ; gain = 0.000

  270. INFO: [Project 1-111] Unisim Transformation Summary:

  271. No Unisim elements were transformed.

  272. 

  273. INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...

  274. INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v"

  275. INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v

  276. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  277. INFO: [USF-XSim-2] XSim::Compile design

  278. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  279. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  280. INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib

  281. INFO: [VRFC 10-311] analyzing module pwm_test

  282. INFO: [VRFC 10-311] analyzing module glbl

  283. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  284. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  285. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  286. INFO: [USF-XSim-69] 'compile' step finished in '4' seconds

  287. INFO: [USF-XSim-3] XSim::Elaborate design

  288. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  289. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  290. Vivado Simulator v2021.2

  291. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  292. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  293. Using 2 slave threads.

  294. Starting static elaboration

  295. Pass Through NonSizing Optimizer

  296. Completed static elaboration

  297. Starting simulation data flow analysis

  298. Completed simulation data flow analysis

  299. Time Resolution for simulation is 1ps

  300. Compiling package std.standard

  301. Compiling package std.textio

  302. Compiling package ieee.std_logic_1164

  303. Compiling package vl.vl_types

  304. Compiling module xil_defaultlib.glbl

  305. Compiling module unisims_ver.BUFG

  306. Compiling module unisims_ver.IBUF

  307. Compiling module unisims_ver.x_lut1_mux2

  308. Compiling module unisims_ver.LUT1(INIT=2'b01)

  309. Compiling module unisims_ver.FDCE_default

  310. Compiling module unisims_ver.CARRY4

  311. Compiling module unisims_ver.OBUF

  312. Compiling module unisims_ver.latchsre_ldce

  313. Compiling module unisims_ver.LDCE

  314. Compiling module unisims_ver.x_lut2_mux4

  315. Compiling module unisims_ver.LUT2

  316. Compiling module xil_defaultlib.pwm_test

  317. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  318. Built simulation snapshot pwm_test_db_func_synth

  319. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  320. INFO: [USF-XSim-4] XSim::Simulate design

  321. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  322. INFO: [USF-XSim-98] *** Running xsim

  323.    with args "pwm_test_db_func_synth -key {Post-Synthesis:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -log {simulate.log}"

  324. INFO: [USF-XSim-8] Loading simulator feature

  325. Time resolution is 1 ps

  326. source pwm_test_db.tcl

  327. # set curr_wave [current_wave_config]

  328. # if { [string length $curr_wave] == 0 } {

  329. #   if { [llength [get_objects]] > 0} {

  330. #     add_wave /

  331. #     set_property needs_save false [current_wave_config]

  332. #   } else {

  333. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  334. #   }

  335. # }

  336. # run 1000ns

  337. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_func_synth' loaded.

  338. INFO: [USF-XSim-97] XSim simulation ran for 1000ns

  339. launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:11 . Memory (MB): peak = 2560.469 ; gain = 181.691

  340. relaunch_sim

  341. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  342. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  343. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  344. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  345. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  346. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  347. INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...

  348. INFO: [SIM-utils-25] write_verilog -mode funcsim -nolib -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v"

  349. INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v

  350. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  351. INFO: [USF-XSim-2] XSim::Compile design

  352. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  353. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  354. INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim/pwm_test_db_func_synth.v" into library xil_defaultlib

  355. INFO: [VRFC 10-311] analyzing module pwm_test

  356. INFO: [VRFC 10-311] analyzing module glbl

  357. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  358. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  359. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  360. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  361. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  362. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  363. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  364. INFO: [USF-XSim-3] XSim::Elaborate design

  365. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  366. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  367. Vivado Simulator v2021.2

  368. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  369. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  370. Using 2 slave threads.

  371. Starting static elaboration

  372. Pass Through NonSizing Optimizer

  373. Completed static elaboration

  374. Starting simulation data flow analysis

  375. Completed simulation data flow analysis

  376. Time Resolution for simulation is 1ps

  377. Compiling package std.standard

  378. Compiling package std.textio

  379. Compiling package ieee.std_logic_1164

  380. Compiling package vl.vl_types

  381. Compiling module xil_defaultlib.glbl

  382. Compiling module unisims_ver.BUFG

  383. Compiling module unisims_ver.IBUF

  384. Compiling module unisims_ver.x_lut1_mux2

  385. Compiling module unisims_ver.LUT1(INIT=2'b01)

  386. Compiling module unisims_ver.FDCE_default

  387. Compiling module unisims_ver.CARRY4

  388. Compiling module unisims_ver.OBUF

  389. Compiling module unisims_ver.latchsre_ldce

  390. Compiling module unisims_ver.LDCE

  391. Compiling module unisims_ver.x_lut2_mux4

  392. Compiling module unisims_ver.LUT2

  393. Compiling module xil_defaultlib.pwm_test

  394. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  395. Built simulation snapshot pwm_test_db_func_synth

  396. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  397. Time resolution is 1 ps

  398. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2565.645 ; gain = 0.000

  399. relaunch_sim

  400. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  401. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  402. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  403. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  404. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  405. INFO: [USF-XSim-2] XSim::Compile design

  406. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  407. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  408. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  409. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  410. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  411. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  412. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  413. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  414. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  415. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  416. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  417. INFO: [USF-XSim-3] XSim::Elaborate design

  418. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  419. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  420. Vivado Simulator v2021.2

  421. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  422. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  423. Using 2 slave threads.

  424. Starting static elaboration

  425. Pass Through NonSizing Optimizer

  426. Completed static elaboration

  427. Starting simulation data flow analysis

  428. Completed simulation data flow analysis

  429. Time Resolution for simulation is 1ps

  430. Compiling package std.standard

  431. Compiling package std.textio

  432. Compiling package ieee.std_logic_1164

  433. Compiling package vl.vl_types

  434. Compiling module xil_defaultlib.glbl

  435. Compiling module unisims_ver.BUFG

  436. Compiling module unisims_ver.IBUF

  437. Compiling module unisims_ver.x_lut1_mux2

  438. Compiling module unisims_ver.LUT1(INIT=2'b01)

  439. Compiling module unisims_ver.FDCE_default

  440. Compiling module unisims_ver.CARRY4

  441. Compiling module unisims_ver.OBUF

  442. Compiling module unisims_ver.latchsre_ldce

  443. Compiling module unisims_ver.LDCE

  444. Compiling module unisims_ver.x_lut2_mux4

  445. Compiling module unisims_ver.LUT2

  446. Compiling module xil_defaultlib.pwm_test

  447. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  448. Built simulation snapshot pwm_test_db_func_synth

  449. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  450. Time resolution is 1 ps

  451. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2569.133 ; gain = 3.281

  452. current_wave_config {Untitled 2}

  453. Untitled 2

  454. add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 

  455. relaunch_sim

  456. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  457. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  458. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  459. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  460. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  461. INFO: [USF-XSim-2] XSim::Compile design

  462. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  463. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  464. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  465. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  466. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  467. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  468. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  469. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  470. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  471. INFO: [USF-XSim-3] XSim::Elaborate design

  472. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  473. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  474. Vivado Simulator v2021.2

  475. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  476. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  477. Using 2 slave threads.

  478. Starting static elaboration

  479. Pass Through NonSizing Optimizer

  480. Completed static elaboration

  481. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  482. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  483. Time resolution is 1 ps

  484. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2569.211 ; gain = 0.000

  485. current_wave_config {Untitled 2}

  486. Untitled 2

  487. add_wave {{/pwm_test_db/uut/\count[0]_i_2_n_0 }} 

  488. launch_simulation

  489. Command: launch_simulation 

  490. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  491. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  492. relaunch_sim

  493. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  494. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  495. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  496. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  497. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  498. INFO: [USF-XSim-2] XSim::Compile design

  499. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  500. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  501. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  502. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  503. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  504. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  505. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  506. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  507. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  508. INFO: [USF-XSim-3] XSim::Elaborate design

  509. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  510. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  511. Vivado Simulator v2021.2

  512. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  513. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  514. Using 2 slave threads.

  515. Starting static elaboration

  516. Pass Through NonSizing Optimizer

  517. Completed static elaboration

  518. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  519. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  520. Time resolution is 1 ps

  521. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 2635.207 ; gain = 0.000

  522. relaunch_sim

  523. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  524. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  525. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  526. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  527. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  528. INFO: [USF-XSim-2] XSim::Compile design

  529. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  530. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  531. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  532. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  533. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  534. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  535. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  536. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  537. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  538. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  539. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  540. INFO: [USF-XSim-3] XSim::Elaborate design

  541. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  542. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  543. Vivado Simulator v2021.2

  544. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  545. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  546. Using 2 slave threads.

  547. Starting static elaboration

  548. Pass Through NonSizing Optimizer

  549. Completed static elaboration

  550. Starting simulation data flow analysis

  551. Completed simulation data flow analysis

  552. Time Resolution for simulation is 1ps

  553. Compiling package std.standard

  554. Compiling package std.textio

  555. Compiling package ieee.std_logic_1164

  556. Compiling package vl.vl_types

  557. Compiling module xil_defaultlib.glbl

  558. Compiling module unisims_ver.BUFG

  559. Compiling module unisims_ver.IBUF

  560. Compiling module unisims_ver.x_lut1_mux2

  561. Compiling module unisims_ver.LUT1(INIT=2'b01)

  562. Compiling module unisims_ver.FDCE_default

  563. Compiling module unisims_ver.CARRY4

  564. Compiling module unisims_ver.OBUF

  565. Compiling module unisims_ver.latchsre_ldce

  566. Compiling module unisims_ver.LDCE

  567. Compiling module unisims_ver.x_lut2_mux4

  568. Compiling module unisims_ver.LUT2

  569. Compiling module xil_defaultlib.pwm_test

  570. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  571. Built simulation snapshot pwm_test_db_func_synth

  572. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  573. Time resolution is 1 ps

  574. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 2847.305 ; gain = 0.000

  575. current_wave_config {Untitled 2}

  576. Untitled 2

  577. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_2 }} 

  578. relaunch_sim

  579. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  580. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  581. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  582. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  583. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  584. INFO: [USF-XSim-2] XSim::Compile design

  585. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  586. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  587. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  588. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  589. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  590. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  591. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  592. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  593. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  594. INFO: [USF-XSim-3] XSim::Elaborate design

  595. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  596. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  597. Vivado Simulator v2021.2

  598. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  599. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  600. Using 2 slave threads.

  601. Starting static elaboration

  602. Pass Through NonSizing Optimizer

  603. Completed static elaboration

  604. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  605. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds

  606. Time resolution is 1 ps

  607. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3078.270 ; gain = 0.000

  608. current_wave_config {Untitled 2}

  609. Untitled 2

  610. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_1 }} 

  611. current_wave_config {Untitled 2}

  612. Untitled 2

  613. add_wave {{/pwm_test_db/uut/\count_reg[0]_i_1_n_3 }} 

  614. relaunch_sim

  615. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  616. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  617. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  618. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  619. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  620. INFO: [USF-XSim-2] XSim::Compile design

  621. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  622. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  623. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  624. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  625. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  626. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  627. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  628. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  629. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  630. INFO: [USF-XSim-3] XSim::Elaborate design

  631. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  632. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  633. Vivado Simulator v2021.2

  634. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  635. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  636. Using 2 slave threads.

  637. Starting static elaboration

  638. Pass Through NonSizing Optimizer

  639. Completed static elaboration

  640. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  641. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  642. Time resolution is 1 ps

  643. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  644. current_wave_config {Untitled 2}

  645. Untitled 2

  646. add_wave {{/pwm_test_db/uut}} 

  647. relaunch_sim

  648. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  649. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  650. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  651. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  652. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  653. INFO: [USF-XSim-2] XSim::Compile design

  654. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  655. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  656. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  657. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  658. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  659. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  660. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  661. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  662. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  663. INFO: [USF-XSim-3] XSim::Elaborate design

  664. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  665. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  666. Vivado Simulator v2021.2

  667. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  668. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  669. Using 2 slave threads.

  670. Starting static elaboration

  671. Pass Through NonSizing Optimizer

  672. Completed static elaboration

  673. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  674. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  675. Time resolution is 1 ps

  676. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  677. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}

  678. add_files -fileset sim_1 -norecurse C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg

  679. set_property xsim.view C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg [get_filesets sim_1]

  680. set_property -name {xsim.simulate.runtime} -value {5000 ms} -objects [get_filesets sim_1]

  681. relaunch_sim

  682. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  683. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  684. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  685. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  686. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  687. INFO: [USF-XSim-2] XSim::Compile design

  688. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  689. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  690. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  691. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  692. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  693. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  694. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  695. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  696. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  697. INFO: [USF-XSim-3] XSim::Elaborate design

  698. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  699. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  700. Vivado Simulator v2021.2

  701. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  702. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  703. Using 2 slave threads.

  704. Starting static elaboration

  705. Pass Through NonSizing Optimizer

  706. Completed static elaboration

  707. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  708. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  709. Time resolution is 1 ps

  710. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  711. relaunch_sim

  712. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  713. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  714. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  715. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  716. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  717. INFO: [USF-XSim-2] XSim::Compile design

  718. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  719. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  720. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  721. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  722. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  723. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  724. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  725. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  726. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  727. INFO: [USF-XSim-3] XSim::Elaborate design

  728. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  729. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  730. Vivado Simulator v2021.2

  731. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  732. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  733. Using 2 slave threads.

  734. Starting static elaboration

  735. Pass Through NonSizing Optimizer

  736. Completed static elaboration

  737. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  738. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  739. Time resolution is 1 ps

  740. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  741. launch_simulation

  742. Command: launch_simulation 

  743. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  744. boost::filesystem::remove: Der Prozess kann nicht auf die Datei zugreifen, da sie von einem anderen Prozess verwendet wird: "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log"

  745. relaunch_sim

  746. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  747. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  748. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  749. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  750. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  751. INFO: [USF-XSim-2] XSim::Compile design

  752. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  753. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  754. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  755. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  756. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  757. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  758. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  759. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  760. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  761. INFO: [USF-XSim-3] XSim::Elaborate design

  762. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  763. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  764. Vivado Simulator v2021.2

  765. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  766. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  767. Using 2 slave threads.

  768. Starting static elaboration

  769. Pass Through NonSizing Optimizer

  770. Completed static elaboration

  771. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  772. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  773. Time resolution is 1 ps

  774. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 3895.711 ; gain = 0.000

  775. reset_run synth_1

  776. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/utils_1/imports/synth_1/pwm_test.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/pwm_test.dcp

  777. WARNING: [Vivado 12-1017] Problems encountered:

  778. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1

  779. 

  780. launch_runs synth_1 -jobs 6

  781. [Wed Mar 16 20:50:10 2022] Launched synth_1...

  782. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.runs/synth_1/runme.log

  783. relaunch_sim

  784. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  785. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  786. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  787. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  788. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  789. INFO: [USF-XSim-2] XSim::Compile design

  790. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  791. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  792. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  793. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  794. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  795. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  796. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  797. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  798. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  799. INFO: [USF-XSim-3] XSim::Elaborate design

  800. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  801. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  802. Vivado Simulator v2021.2

  803. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  804. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  805. Using 2 slave threads.

  806. Starting static elaboration

  807. Pass Through NonSizing Optimizer

  808. Completed static elaboration

  809. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  810. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds

  811. Time resolution is 1 ps

  812. relaunch_sim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  813. relaunch_sim

  814. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  815. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  816. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  817. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  818. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  819. INFO: [USF-XSim-2] XSim::Compile design

  820. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  821. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  822. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  823. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  824. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  825. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  826. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  827. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  828. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  829. INFO: [USF-XSim-3] XSim::Elaborate design

  830. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  831. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  832. Vivado Simulator v2021.2

  833. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  834. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  835. Using 2 slave threads.

  836. Starting static elaboration

  837. Pass Through NonSizing Optimizer

  838. Completed static elaboration

  839. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  840. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  841. Time resolution is 1 ps

  842. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  843. reset_simulation -simset sim_1 -mode behavioral

  844. INFO: [Vivado 12-2266] Removing simulation data...

  845. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_behav.wdb

  846. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/simulate.log

  847. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb

  848. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsim.xdbg

  849. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimcrash.log

  850. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimk.exe

  851. WARNING: [Vivado 12-3661] Failed to remove file:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav/xsimkernel.log

  852. WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_behav

  853. WARNING: [Vivado 12-4421] Failed to remove directory:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir

  854. INFO: [Vivado 12-2267] Reset complete

  855. relaunch_sim

  856. Command: launch_simulation -step compile -simset sim_1 -mode post-synthesis -type functional

  857. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  858. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  859. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  860. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  861. INFO: [USF-XSim-2] XSim::Compile design

  862. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  863. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  864. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  865. INFO: [USF-XSim-69] 'compile' step finished in '4' seconds

  866. Command: launch_simulation -step elaborate -simset sim_1 -mode post-synthesis -type functional

  867. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  868. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  869. INFO: [Vivado 12-5682] Launching post-synthesis functional simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  870. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  871. INFO: [USF-XSim-3] XSim::Elaborate design

  872. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/func/xsim'

  873. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  874. Vivado Simulator v2021.2

  875. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  876. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L secureip --snapshot pwm_test_db_func_synth xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  877. Using 2 slave threads.

  878. Starting static elaboration

  879. Pass Through NonSizing Optimizer

  880. Completed static elaboration

  881. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  882. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds

  883. Time resolution is 1 ps

  884. relaunch_sim: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3895.711 ; gain = 0.000

  885. reset_simulation -simset sim_1 -mode post-synthesis -type timing

  886. close_design

  887. launch_simulation -mode post-synthesis -type timing

  888. Command: launch_simulation  -mode post-synthesis -type timing

  889. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  890. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  891. INFO: [Vivado 12-5682] Launching post-synthesis timing simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'

  892. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  893. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  894. Design is defaulting to impl run constrset: constrs_1

  895. Design is defaulting to synth run part: xc7z010clg400-1

  896. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3895.711 ; gain = 0.000

  897. INFO: [Netlist 29-17] Analyzing 16 Unisim elements for replacement

  898. INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds

  899. INFO: [Project 1-479] Netlist was created with Vivado 2021.2

  900. INFO: [Project 1-570] Preparing netlist for logic optimization

  901. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  902. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3895.711 ; gain = 0.000

  903. INFO: [Project 1-111] Unisim Transformation Summary:

  904. No Unisim elements were transformed.

  905. 

  906. INFO: [SIM-utils-24] Writing simulation netlist file for design 'synth_1'...

  907. INFO: [SIM-utils-25] write_verilog -mode timesim -nolib -sdf_anno true -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v"

  908. INFO: [SIM-utils-27] Writing SDF file...

  909. INFO: [SIM-utils-28] write_sdf -mode timesim -process_corner slow -force -file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf"

  910. INFO: [SIM-utils-36] Netlist generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v

  911. INFO: [SIM-utils-37] SDF generated:C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.sdf

  912. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  913. INFO: [USF-XSim-2] XSim::Compile design

  914. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'

  915. "xvlog --incr --relax -prj pwm_test_db_vlog.prj"

  916. INFO: [VRFC 10-2263] Analyzing Verilog file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim/pwm_test_db_time_synth.v" into library xil_defaultlib

  917. INFO: [VRFC 10-311] analyzing module pwm_test

  918. INFO: [VRFC 10-311] analyzing module glbl

  919. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  920. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  921. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  922. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  923. INFO: [USF-XSim-3] XSim::Elaborate design

  924. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'

  925. "xelab --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log"

  926. Vivado Simulator v2021.2

  927. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  928. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 --maxdelay -L xil_defaultlib -L simprims_ver -L secureip --snapshot pwm_test_db_time_synth -transport_int_delays -pulse_r 0 -pulse_int_r 0 -pulse_e 0 -pulse_int_e 0 xil_defaultlib.pwm_test_db xil_defaultlib.glbl -log elaborate.log 

  929. Using 2 slave threads.

  930. Starting static elaboration

  931. Pass Through NonSizing Optimizer

  932. Completed static elaboration

  933. Starting simulation data flow analysis

  934. Completed simulation data flow analysis

  935. INFO: [XSIM 43-3451] SDF backannotation process started with SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".

  936. INFO: [XSIM 43-3452] SDF backannotation was successful for SDF file "pwm_test_db_time_synth.sdf", for root module "pwm_test_db/uut".

  937. Time Resolution for simulation is 1ps

  938. Compiling package std.standard

  939. Compiling package std.textio

  940. Compiling package ieee.std_logic_1164

  941. Compiling package vl.vl_types

  942. Compiling module xil_defaultlib.glbl

  943. Compiling module simprims_ver.BUFG

  944. Compiling module simprims_ver.IBUF

  945. Compiling module simprims_ver.x_lut1_mux2

  946. Compiling module simprims_ver.LUT1(INIT=2'b01)

  947. Compiling module simprims_ver.FDCE_default

  948. Compiling module simprims_ver.CARRY4

  949. Compiling module simprims_ver.OBUF

  950. Compiling module simprims_ver.latchsre_ldce

  951. Compiling module simprims_ver.LDCE

  952. Compiling module simprims_ver.x_lut2_mux4

  953. Compiling module simprims_ver.LUT2

  954. Compiling module xil_defaultlib.pwm_test

  955. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  956. Built simulation snapshot pwm_test_db_time_synth

  957. run_program: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 3895.711 ; gain = 0.000

  958. INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds

  959. INFO: [USF-XSim-4] XSim::Simulate design

  960. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/Coraz7_Test.sim/sim_1/synth/timing/xsim'

  961. INFO: [USF-XSim-98] *** Running xsim

  962.    with args "pwm_test_db_time_synth -key {Post-Synthesis:sim_1:Timing:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  963. INFO: [USF-XSim-8] Loading simulator feature

  964. Time resolution is 1 ps

  965. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg

  966. source pwm_test_db.tcl

  967. # set curr_wave [current_wave_config]

  968. # if { [string length $curr_wave] == 0 } {

  969. #   if { [llength [get_objects]] > 0} {

  970. #     add_wave /

  971. #     set_property needs_save false [current_wave_config]

  972. #   } else {

  973. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  974. #   }

  975. # }

  976. # run 5000 ms

  977. INFO: [Common 17-41] Interrupt caught. Command should exit soon.

  978. run: Time (s): cpu = 00:00:27 ; elapsed = 00:07:42 . Memory (MB): peak = 3895.711 ; gain = 0.000

  979. INFO: [Common 17-344] 'run' was cancelled

  980. INFO: [Common 17-344] 'source' was cancelled

  981. xsim: Time (s): cpu = 00:00:28 ; elapsed = 00:07:44 . Memory (MB): peak = 3895.711 ; gain = 0.000

  982. INFO: [Common 17-344] 'xsim' was cancelled

  983. INFO: [Vivado 12-5357] 'simulate' step aborted

  984. launch_simulation: Time (s): cpu = 00:00:35 ; elapsed = 00:07:56 . Memory (MB): peak = 3895.711 ; gain = 0.000

  985. INFO: [Common 17-344] 'launch_simulation' was cancelled

  986. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Coraz7_Test/pwm_test_db_func_synth.wcfg}

  987. close_sim

  988. INFO: xsimkernel Simulation Memory Usage: 20776 KB (Peak: 20776 KB), Simulation CPU Usage: 461827 ms

  989. INFO: [Simtcl 6-16] Simulation closed

  990. current_sim simulation_2

  991. close_sim

  992. INFO: [Simtcl 6-16] Simulation closed

  993. close_sim

  994. INFO: [Simtcl 6-16] Simulation closed

  995. exit

  996. INFO: [Common 17-206] Exiting Vivado at Wed Mar 16 21:11:02 2022...