Autotuning simuliert

This commit is contained in:
Felix Stamm 2022-06-01 16:22:47 +02:00
parent 0ec72e8d48
commit 6e2b58f3d4
43 changed files with 146 additions and 103 deletions

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version:1 version:1
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6d6f64655f636f756e7465727c4755494d6f6465:40 6d6f64655f636f756e7465727c4755494d6f6465:42
eof: eof:

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@ -38,7 +38,7 @@ version:1
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73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313336392e3636384d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313337342e3832384d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3130392e3431384d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3131332e3831364d42:00:00
eof:3780437457 eof:1125365045

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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

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@ -0,0 +1,9 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

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<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
</Parameters>
</Runs>

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@ -1,5 +1,5 @@
<?xml version="1.0"?> <?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0"> <ProcessHandle Version="1" Minor="0">
<Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="18920" HostCore="12" HostMemory="016927088640"> <Process Command="vivado.bat" Owner="Felix" Host="DESKTOP-PAACOM8" Pid="21876" HostCore="12" HostMemory="016927088640">
</Process> </Process>
</ProcessHandle> </ProcessHandle>

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<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1654026672" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp"> <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1654092141" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp">
<File Type="PA-TCL" Name="regler.tcl"/> <File Type="PA-TCL" Name="regler.tcl"/>
<File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/> <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/>
<File Type="REPORTS-TCL" Name="regler_reports.tcl"/> <File Type="REPORTS-TCL" Name="regler_reports.tcl"/>

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@ -13,7 +13,7 @@ version:1
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313731:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:313736:00:00
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
@ -28,4 +28,4 @@ version:1
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70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
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eof:1339287396 eof:660781908

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@ -2,8 +2,8 @@
# Vivado v2021.2 (64-bit) # Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue May 31 21:51:15 2022 # Start of session at: Wed Jun 1 16:02:24 2022
# Process ID: 7140 # Process ID: 11440
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds
@ -11,7 +11,7 @@
# Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB
#----------------------------------------------------------- #-----------------------------------------------------------
source regler.tcl -notrace source regler.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.012 ; gain = 6.973
Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes INFO: [Vivado 12-7989] Please ensure there are no constraint changes
@ -24,9 +24,9 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 7236 INFO: [Synth 8-7075] Helper process launched with PID 14456
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51]
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115]
@ -43,18 +43,18 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
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Start Handling Custom Attributes Start Handling Custom Attributes
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Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
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Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1261.012 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints Processing XDC Constraints
@ -65,31 +65,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1279.703 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1279.703 ; gain = 0.000
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
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Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7z010clg400-1 Loading part: xc7z010clg400-1
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints Start Applying 'set_property' XDC Constraints
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--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1279.703 ; gain = 18.691
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Start RTL Component Statistics Start RTL Component Statistics
@ -223,7 +223,7 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1279.703 ; gain = 18.691
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Start ROM, RAM, DSP, Shift Register and Retiming Reporting Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -271,19 +271,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints Start Applying XDC Timing Constraints
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Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1291.957 ; gain = 30.945
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Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1302.121 ; gain = 41.109
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.969 ; gain = 99.957
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start IO Insertion Start IO Insertion
@ -301,37 +301,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
@ -361,19 +361,19 @@ Report Cell Usage:
|12 |OBUF | 64| |12 |OBUF | 64|
+------+--------+------+ +------+--------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:47 . Memory (MB): peak = 1374.828 ; gain = 95.125
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1386.875 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1390.559 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
@ -381,7 +381,7 @@ Synth Design complete, checksum: 6d8170b6
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1390.559 ; gain = 129.547
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... INFO: [Common 17-206] Exiting Vivado at Wed Jun 1 16:03:33 2022...

View File

@ -1,7 +1,7 @@
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021 | Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
| Date : Tue May 31 21:52:26 2022 | Date : Wed Jun 1 16:03:33 2022
| Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200) | Host : DESKTOP-PAACOM8 running 64-bit major release (build 9200)
| Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb | Command : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
| Design : regler | Design : regler

View File

@ -10,7 +10,7 @@
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
source regler.tcl -notrace source regler.tcl -notrace
create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1260.250 ; gain = 7.859 create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1261.012 ; gain = 6.973
Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes INFO: [Vivado 12-7989] Please ensure there are no constraint changes
@ -23,9 +23,9 @@ WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis b
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 7236 INFO: [Synth 8-7075] Helper process launched with PID 14456
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1260.250 ; gain = 0.000 Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51] INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:51]
WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115] WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed. [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:115]
@ -42,18 +42,18 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1260.250 ; gain = 0.000 Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.012 ; gain = 0.000
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 1260.250 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 1261.012 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints Processing XDC Constraints
@ -64,31 +64,31 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1277.531 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1279.703 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1277.531 ; gain = 0.000 Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1279.703 ; gain = 0.000
WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate} INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Loading Part and Timing Information Start Loading Part and Timing Information
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Loading part: xc7z010clg400-1 Loading part: xc7z010clg400-1
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints Start Applying 'set_property' XDC Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:18 ; elapsed = 00:00:18 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:15 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start RTL Component Statistics Start RTL Component Statistics
@ -222,7 +222,7 @@ WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has
WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load
WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 1277.531 ; gain = 17.281 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 1279.703 ; gain = 18.691
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -270,19 +270,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints Start Applying XDC Timing Constraints
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1290.168 ; gain = 29.918 Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:38 ; elapsed = 00:00:39 . Memory (MB): peak = 1291.957 ; gain = 30.945
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Timing Optimization Start Timing Optimization
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1300.332 ; gain = 40.082 Finished Timing Optimization : Time (s): cpu = 00:00:39 ; elapsed = 00:00:40 . Memory (MB): peak = 1302.121 ; gain = 41.109
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Technology Mapping Start Technology Mapping
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:44 . Memory (MB): peak = 1358.793 ; gain = 98.543 Finished Technology Mapping : Time (s): cpu = 00:00:42 ; elapsed = 00:00:43 . Memory (MB): peak = 1360.969 ; gain = 99.957
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start IO Insertion Start IO Insertion
@ -300,37 +300,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup Finished Final Netlist Cleanup
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished IO Insertion : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Instances Start Renaming Generated Instances
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Instances : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy Start Rebuilding User Hierarchy
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Ports Start Renaming Generated Ports
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Ports : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Handling Custom Attributes Start Handling Custom Attributes
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Handling Custom Attributes : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Renaming Generated Nets Start Renaming Generated Nets
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Renaming Generated Nets : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Start Writing Synthesis Report Start Writing Synthesis Report
@ -360,19 +360,19 @@ Report Cell Usage:
|12 |OBUF | 64| |12 |OBUF | 64|
+------+--------+------+ +------+--------+------+
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Finished Writing Synthesis Report : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
--------------------------------------------------------------------------------- ---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:40 ; elapsed = 00:00:49 . Memory (MB): peak = 1369.668 ; gain = 92.137 Synthesis Optimization Runtime : Time (s): cpu = 00:00:39 ; elapsed = 00:00:47 . Memory (MB): peak = 1374.828 ; gain = 95.125
Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1369.668 ; gain = 109.418 Synthesis Optimization Complete : Time (s): cpu = 00:00:48 ; elapsed = 00:00:49 . Memory (MB): peak = 1374.828 ; gain = 113.816
INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.193 . Memory (MB): peak = 1377.176 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.235 . Memory (MB): peak = 1386.875 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement INFO: [Netlist 29-17] Analyzing 2858 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning. WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives. Please consider enabling hierarchy in synthesis if you want to do floorplanning.
INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1377.863 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1390.559 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary: INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed. No Unisim elements were transformed.
@ -380,7 +380,7 @@ Synth Design complete, checksum: 6d8170b6
INFO: [Common 17-83] Releasing license: Synthesis INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered. 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully synth_design completed successfully
synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:01:00 . Memory (MB): peak = 1377.863 ; gain = 117.613 synth_design: Time (s): cpu = 00:00:57 ; elapsed = 00:00:58 . Memory (MB): peak = 1390.559 ; gain = 129.547
INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Tue May 31 21:52:26 2022... INFO: [Common 17-206] Exiting Vivado at Wed Jun 1 16:03:33 2022...

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@ -2,8 +2,8 @@
# Vivado v2021.2 (64-bit) # Vivado v2021.2 (64-bit)
# SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
# IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021
# Start of session at: Tue May 31 21:51:15 2022 # Start of session at: Wed Jun 1 16:02:24 2022
# Process ID: 7140 # Process ID: 11440
# Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1
# Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl
# Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds

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@ -6,7 +6,7 @@ REM Filename : compile.bat
REM Simulator : Xilinx Vivado Simulator REM Simulator : Xilinx Vivado Simulator
REM Description : Script for compiling the simulation design source files REM Description : Script for compiling the simulation design source files
REM REM
REM Generated by Vivado on Tue May 31 21:54:27 +0200 2022 REM Generated by Vivado on Wed Jun 01 16:04:36 +0200 2022
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
REM REM
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

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@ -1,2 +1,2 @@
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [VRFC 10-3107] analyzing entity 'autoTuning'

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@ -6,7 +6,7 @@ REM Filename : elaborate.bat
REM Simulator : Xilinx Vivado Simulator REM Simulator : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design REM Description : Script for elaborating the compiled design
REM REM
REM Generated by Vivado on Tue May 31 21:54:29 +0200 2022 REM Generated by Vivado on Wed Jun 01 16:04:38 +0200 2022
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
REM REM
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

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@ -6,7 +6,7 @@ REM Filename : simulate.bat
REM Simulator : Xilinx Vivado Simulator REM Simulator : Xilinx Vivado Simulator
REM Description : Script for simulating the design by launching the simulator REM Description : Script for simulating the design by launching the simulator
REM REM
REM Generated by Vivado on Tue May 31 21:54:32 +0200 2022 REM Generated by Vivado on Wed Jun 01 16:04:41 +0200 2022
REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021
REM REM
REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

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@ -54,22 +54,23 @@
#endif #endif
typedef void (*funcp)(char *, char *); typedef void (*funcp)(char *, char *);
extern int main(int, char**); extern int main(int, char**);
IKI_DLLESPEC extern void execute_52(char*, char *);
IKI_DLLESPEC extern void execute_53(char*, char *); IKI_DLLESPEC extern void execute_53(char*, char *);
IKI_DLLESPEC extern void execute_47(char*, char *); IKI_DLLESPEC extern void execute_54(char*, char *);
IKI_DLLESPEC extern void execute_49(char*, char *); IKI_DLLESPEC extern void execute_48(char*, char *);
IKI_DLLESPEC extern void execute_51(char*, char *); IKI_DLLESPEC extern void execute_50(char*, char *);
IKI_DLLESPEC extern void execute_52(char*, char *);
IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned); IKI_DLLESPEC extern void transaction_0(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned); IKI_DLLESPEC extern void transaction_1(char*, char*, unsigned, unsigned, unsigned);
IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[8] = {(funcp)execute_52, (funcp)execute_53, (funcp)execute_47, (funcp)execute_49, (funcp)execute_51, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback}; IKI_DLLESPEC extern void transaction_16(char*, char*, unsigned, unsigned, unsigned);
const int NumRelocateId= 8; funcp funcTab[9] = {(funcp)execute_53, (funcp)execute_54, (funcp)execute_48, (funcp)execute_50, (funcp)execute_52, (funcp)transaction_0, (funcp)transaction_1, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_16};
const int NumRelocateId= 9;
void relocate(char *dp) void relocate(char *dp)
{ {
iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 8); iki_relocate(dp, "xsim.dir/pwm_test_db_behav/xsim.reloc", (void **)funcTab, 9);
iki_vhdl_file_variable_register(dp + 6952); iki_vhdl_file_variable_register(dp + 6992);
iki_vhdl_file_variable_register(dp + 7008); iki_vhdl_file_variable_register(dp + 7048);
/*Populate the transaction function pointer field in the whole net structure */ /*Populate the transaction function pointer field in the whole net structure */

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@ -1,6 +1,6 @@
{ {
crc : 15251868591865205496 , crc : 8097898048764610212 ,
ccp_crc : 0 , ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" ,
buildDate : "Oct 19 2021" , buildDate : "Oct 19 2021" ,

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@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=157 SCOPE_NAME_COLUMN_WIDTH=157
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=156 OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=49 OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75 OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75 PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75 PROCESS_TYPE_COLUMN_WIDTH=75

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@ -1,4 +1,7 @@
Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 50859 Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_behav.wdb -simrunnum 0 -socket 57302
Design successfully loaded Design successfully loaded
Design Loading Memory Usage: 7440 KB (Peak: 7440 KB) Design Loading Memory Usage: 7444 KB (Peak: 7444 KB)
Design Loading CPU Usage: 15 ms Design Loading CPU Usage: 15 ms
Simulation completed
Simulation Memory Usage: 15968 KB (Peak: 15968 KB)
Simulation CPU Usage: 9640 ms

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@ -2,7 +2,7 @@
2020.2 2020.2
Oct 19 2021 Oct 19 2021
03:16:22 03:16:22
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1654026861,vhdl,,,,pwm_test_db,,,,,,,, C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1654085243,vhdl,,,,pwm_test_db,,,,,,,,
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd,1654026641,vhdl,,,,autotuning,,,,,,,, C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd,1654092136,vhdl,,,,autotuning,,,,,,,,
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1653978411,vhdl,,,,pt1,,,,,,,, C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1654085243,vhdl,,,,pt1,,,,,,,,
C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1653978349,vhdl,,,,regler,,,,,,,, C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1654085243,vhdl,,,,regler,,,,,,,,

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@ -1,2 +1,2 @@
INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/autoTuning.vhd" into library xil_defaultlib
INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' INFO: [VRFC 10-3107] analyzing entity 'autoTuning'

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@ -116,6 +116,8 @@ if(rising_edge(clk)) then
end if; end if;
else else
if (falling_edge(start_Tuning)) then
-- autoTuning beenden -- autoTuning beenden
regler_bruecken <= '0'; regler_bruecken <= '0';
counter := to_signed(0, 64); counter := to_signed(0, 64);
@ -126,7 +128,7 @@ if(rising_edge(clk)) then
dt := duration / to_signed(2000, 64); --schrittweite dt := duration / to_signed(2000, 64); --schrittweite
for i in 1 to 2000 loop for i in 1 to 1999 loop
steigung_last := steigung; steigung_last := steigung;
--steigung := (data(i) - data(i-1)) / dt; --"Richtig" --steigung := (data(i) - data(i-1)) / dt; --"Richtig"
steigung := (data(i) - data(i-1)); steigung := (data(i) - data(i-1));
@ -138,7 +140,7 @@ if(rising_edge(clk)) then
-- y = mx + b -- y = mx + b
b := data(data_pos_wendetangente) - steigung * to_signed(data_pos_wendetangente, 32); b := data(data_pos_wendetangente) - steigung * to_signed(data_pos_wendetangente, 32);
Ks := data(2000); Ks := data(1999);
Tu := -b * dt / steigung; Tu := -b * dt / steigung;
Tg := (Ks - b) * dt / steigung - Tu; Tg := (Ks - b) * dt / steigung - Tu;
@ -148,7 +150,7 @@ if(rising_edge(clk)) then
TV <= to_signed(0, 10); TV <= to_signed(0, 10);
TN <= 4 * Tu; TN <= 4 * Tu;
end if;
end if; end if;
end if; end if;

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@ -56,7 +56,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="zybo-z7-10"/> <Option Name="DSABoardId" Val="zybo-z7-10"/>
<Option Name="WTXSimLaunchSim" Val="173"/> <Option Name="WTXSimLaunchSim" Val="177"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>