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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_18960.backup.log

vivado_18960.backup.log 164KB
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
  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Wed May 18 19:29:49 2022

  6. # Process ID: 18960

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent3712 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

  15. INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

  16. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'

  17. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  18. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  19. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  20. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  21. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  22. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available

  23. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available

  24. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available

  25. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  26. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  27. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  28. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  29. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available

  30. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  31. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  32. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  33. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available

  34. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available

  35. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available

  36. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available

  37. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available

  38. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  39. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  40. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available

  41. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available

  42. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  43. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  44. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  45. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  46. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  47. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  48. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  49. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available

  50. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  51. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  52. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  53. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available

  54. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available

  55. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  56. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  57. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  58. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  59. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  60. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available

  61. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available

  62. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.

  63. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.

  64. Scanning sources...

  65. Finished scanning sources

  66. INFO: [IP_Flow 19-234] Refreshing IP repositories

  67. INFO: [IP_Flow 19-1704] No user IP repositories specified

  68. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.

  69. open_project: Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 1251.465 ; gain = 0.000

  70. update_compile_order -fileset sources_1

  71. reset_run synth_1

  72. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  73. launch_runs synth_1 -jobs 6

  74. [Wed May 18 19:58:12 2022] Launched synth_1...

  75. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  76. launch_simulation

  77. Command: launch_simulation 

  78. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  79. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  80. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  81. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  82. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  83. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  84. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  85. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  86. INFO: [USF-XSim-97] Finding global include files...

  87. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  88. INFO: [USF-XSim-2] XSim::Compile design

  89. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  90. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  91. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  92. INFO: [VRFC 10-3107] analyzing entity 'regler'

  93. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  94. INFO: [USF-XSim-3] XSim::Elaborate design

  95. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  96. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  97. Vivado Simulator v2021.2

  98. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  99. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  100. Using 2 slave threads.

  101. Starting static elaboration

  102. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  103. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  104. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  105. Completed static elaboration

  106. Starting simulation data flow analysis

  107. Completed simulation data flow analysis

  108. Time Resolution for simulation is 1ps

  109. Compiling package std.standard

  110. Compiling package std.textio

  111. Compiling package ieee.std_logic_1164

  112. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  113. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  114. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  115. Built simulation snapshot pwm_test_db_behav

  116. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  117. INFO: [USF-XSim-4] XSim::Simulate design

  118. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  119. INFO: [USF-XSim-98] *** Running xsim

  120.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  121. INFO: [USF-XSim-8] Loading simulator feature

  122. Time resolution is 1 ps

  123. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  124. source pwm_test_db.tcl

  125. # set curr_wave [current_wave_config]

  126. # if { [string length $curr_wave] == 0 } {

  127. #   if { [llength [get_objects]] > 0} {

  128. #     add_wave /

  129. #     set_property needs_save false [current_wave_config]

  130. #   } else {

  131. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  132. #   }

  133. # }

  134. # run 5 s

  135. xsim: Time (s): cpu = 00:00:10 ; elapsed = 00:00:05 . Memory (MB): peak = 1251.465 ; gain = 0.000

  136. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  137. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  138. launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1251.465 ; gain = 0.000

  139. close_sim

  140. INFO: [Simtcl 6-16] Simulation closed

  141. launch_simulation

  142. Command: launch_simulation 

  143. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  144. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  145. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  146. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  147. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  148. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  149. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  150. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  151. INFO: [USF-XSim-97] Finding global include files...

  152. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  153. INFO: [USF-XSim-2] XSim::Compile design

  154. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  155. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  156. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  157. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  158. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  159. INFO: [USF-XSim-3] XSim::Elaborate design

  160. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  161. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  162. Vivado Simulator v2021.2

  163. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  164. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  165. Using 2 slave threads.

  166. Starting static elaboration

  167. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  168. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  169. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  170. Completed static elaboration

  171. Starting simulation data flow analysis

  172. Completed simulation data flow analysis

  173. Time Resolution for simulation is 1ps

  174. Compiling package std.standard

  175. Compiling package std.textio

  176. Compiling package ieee.std_logic_1164

  177. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  178. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  179. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  180. Built simulation snapshot pwm_test_db_behav

  181. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  182. INFO: [USF-XSim-4] XSim::Simulate design

  183. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  184. INFO: [USF-XSim-98] *** Running xsim

  185.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  186. INFO: [USF-XSim-8] Loading simulator feature

  187. Time resolution is 1 ps

  188. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  189. source pwm_test_db.tcl

  190. # set curr_wave [current_wave_config]

  191. # if { [string length $curr_wave] == 0 } {

  192. #   if { [llength [get_objects]] > 0} {

  193. #     add_wave /

  194. #     set_property needs_save false [current_wave_config]

  195. #   } else {

  196. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  197. #   }

  198. # }

  199. # run 5 s

  200. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  201. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  202. launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1251.465 ; gain = 0.000

  203. reset_run synth_1

  204. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  205. WARNING: [Vivado 12-1017] Problems encountered:

  206. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  207. 

  208. launch_runs synth_1 -jobs 6

  209. [Wed May 18 20:04:35 2022] Launched synth_1...

  210. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  211. close_sim

  212. INFO: [Simtcl 6-16] Simulation closed

  213. launch_simulation

  214. Command: launch_simulation 

  215. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  216. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  217. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  218. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  219. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  220. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  221. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  222. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  223. INFO: [USF-XSim-97] Finding global include files...

  224. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  225. INFO: [USF-XSim-2] XSim::Compile design

  226. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  227. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  228. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  229. INFO: [VRFC 10-3107] analyzing entity 'regler'

  230. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  231. INFO: [USF-XSim-3] XSim::Elaborate design

  232. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  233. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  234. Vivado Simulator v2021.2

  235. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  236. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  237. Using 2 slave threads.

  238. Starting static elaboration

  239. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  240. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  241. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  242. Completed static elaboration

  243. Starting simulation data flow analysis

  244. Completed simulation data flow analysis

  245. Time Resolution for simulation is 1ps

  246. Compiling package std.standard

  247. Compiling package std.textio

  248. Compiling package ieee.std_logic_1164

  249. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  250. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  251. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  252. Built simulation snapshot pwm_test_db_behav

  253. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  254. INFO: [USF-XSim-4] XSim::Simulate design

  255. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  256. INFO: [USF-XSim-98] *** Running xsim

  257.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  258. INFO: [USF-XSim-8] Loading simulator feature

  259. Time resolution is 1 ps

  260. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  261. source pwm_test_db.tcl

  262. # set curr_wave [current_wave_config]

  263. # if { [string length $curr_wave] == 0 } {

  264. #   if { [llength [get_objects]] > 0} {

  265. #     add_wave /

  266. #     set_property needs_save false [current_wave_config]

  267. #   } else {

  268. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  269. #   }

  270. # }

  271. # run 5 s

  272. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  273. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  274. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1254.031 ; gain = 0.000

  275. reset_run synth_1

  276. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  277. WARNING: [Vivado 12-1017] Problems encountered:

  278. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  279. 

  280. launch_runs synth_1 -jobs 6

  281. [Wed May 18 20:09:08 2022] Launched synth_1...

  282. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  283. reset_run synth_1

  284. WARNING: [Vivado 12-1017] Problems encountered:

  285. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  286. 

  287. launch_runs synth_1 -jobs 6

  288. [Wed May 18 20:09:25 2022] Launched synth_1...

  289. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  290. close_sim

  291. INFO: [Simtcl 6-16] Simulation closed

  292. launch_simulation

  293. Command: launch_simulation 

  294. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  295. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  296. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  297. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  298. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  299. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  300. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  301. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  302. INFO: [USF-XSim-97] Finding global include files...

  303. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  304. INFO: [USF-XSim-2] XSim::Compile design

  305. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  306. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  307. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  308. INFO: [VRFC 10-3107] analyzing entity 'regler'

  309. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  310. INFO: [USF-XSim-3] XSim::Elaborate design

  311. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  312. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  313. Vivado Simulator v2021.2

  314. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  315. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  316. Using 2 slave threads.

  317. Starting static elaboration

  318. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  319. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  320. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  321. Completed static elaboration

  322. Starting simulation data flow analysis

  323. Completed simulation data flow analysis

  324. Time Resolution for simulation is 1ps

  325. Compiling package std.standard

  326. Compiling package std.textio

  327. Compiling package ieee.std_logic_1164

  328. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  329. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  330. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  331. Built simulation snapshot pwm_test_db_behav

  332. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  333. INFO: [USF-XSim-4] XSim::Simulate design

  334. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  335. INFO: [USF-XSim-98] *** Running xsim

  336.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  337. INFO: [USF-XSim-8] Loading simulator feature

  338. Time resolution is 1 ps

  339. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  340. source pwm_test_db.tcl

  341. # set curr_wave [current_wave_config]

  342. # if { [string length $curr_wave] == 0 } {

  343. #   if { [llength [get_objects]] > 0} {

  344. #     add_wave /

  345. #     set_property needs_save false [current_wave_config]

  346. #   } else {

  347. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  348. #   }

  349. # }

  350. # run 5 s

  351. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  352. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  353. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1255.961 ; gain = 0.000

  354. reset_run synth_1

  355. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  356. WARNING: [Vivado 12-1017] Problems encountered:

  357. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  358. 

  359. launch_runs synth_1 -jobs 6

  360. [Wed May 18 20:13:37 2022] Launched synth_1...

  361. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  362. close_sim

  363. INFO: [Simtcl 6-16] Simulation closed

  364. launch_simulation

  365. Command: launch_simulation 

  366. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  367. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  368. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  369. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  370. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  371. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  372. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  373. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  374. INFO: [USF-XSim-97] Finding global include files...

  375. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  376. INFO: [USF-XSim-2] XSim::Compile design

  377. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  378. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  379. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  380. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  381. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  382. INFO: [USF-XSim-3] XSim::Elaborate design

  383. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  384. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  385. Vivado Simulator v2021.2

  386. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  387. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  388. Using 2 slave threads.

  389. Starting static elaboration

  390. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  391. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  392. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  393. Completed static elaboration

  394. Starting simulation data flow analysis

  395. Completed simulation data flow analysis

  396. Time Resolution for simulation is 1ps

  397. Compiling package std.standard

  398. Compiling package std.textio

  399. Compiling package ieee.std_logic_1164

  400. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  401. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  402. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  403. Built simulation snapshot pwm_test_db_behav

  404. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  405. INFO: [USF-XSim-4] XSim::Simulate design

  406. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  407. INFO: [USF-XSim-98] *** Running xsim

  408.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  409. INFO: [USF-XSim-8] Loading simulator feature

  410. Time resolution is 1 ps

  411. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  412. source pwm_test_db.tcl

  413. # set curr_wave [current_wave_config]

  414. # if { [string length $curr_wave] == 0 } {

  415. #   if { [llength [get_objects]] > 0} {

  416. #     add_wave /

  417. #     set_property needs_save false [current_wave_config]

  418. #   } else {

  419. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  420. #   }

  421. # }

  422. # run 5 s

  423. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  424. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  425. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000

  426. reset_run synth_1

  427. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  428. WARNING: [Vivado 12-1017] Problems encountered:

  429. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  430. 

  431. launch_runs synth_1 -jobs 6

  432. [Wed May 18 20:15:34 2022] Launched synth_1...

  433. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  434. close_sim

  435. INFO: [Simtcl 6-16] Simulation closed

  436. launch_simulation

  437. Command: launch_simulation 

  438. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  439. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  440. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  441. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  442. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  443. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  444. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  445. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  446. INFO: [USF-XSim-97] Finding global include files...

  447. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  448. INFO: [USF-XSim-2] XSim::Compile design

  449. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  450. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  451. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  452. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  453. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  454. INFO: [USF-XSim-3] XSim::Elaborate design

  455. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  456. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  457. Vivado Simulator v2021.2

  458. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  459. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  460. Using 2 slave threads.

  461. Starting static elaboration

  462. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  463. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  464. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  465. Completed static elaboration

  466. Starting simulation data flow analysis

  467. Completed simulation data flow analysis

  468. Time Resolution for simulation is 1ps

  469. Compiling package std.standard

  470. Compiling package std.textio

  471. Compiling package ieee.std_logic_1164

  472. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  473. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  474. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  475. Built simulation snapshot pwm_test_db_behav

  476. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  477. INFO: [USF-XSim-4] XSim::Simulate design

  478. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  479. INFO: [USF-XSim-98] *** Running xsim

  480.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  481. INFO: [USF-XSim-8] Loading simulator feature

  482. Time resolution is 1 ps

  483. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  484. source pwm_test_db.tcl

  485. # set curr_wave [current_wave_config]

  486. # if { [string length $curr_wave] == 0 } {

  487. #   if { [llength [get_objects]] > 0} {

  488. #     add_wave /

  489. #     set_property needs_save false [current_wave_config]

  490. #   } else {

  491. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  492. #   }

  493. # }

  494. # run 5 s

  495. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  496. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  497. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000

  498. reset_run synth_1

  499. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  500. WARNING: [Vivado 12-1017] Problems encountered:

  501. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  502. 

  503. launch_runs synth_1 -jobs 6

  504. [Wed May 18 20:19:22 2022] Launched synth_1...

  505. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  506. close_sim

  507. INFO: [Simtcl 6-16] Simulation closed

  508. launch_simulation

  509. Command: launch_simulation 

  510. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  511. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  512. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  513. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  514. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  515. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  516. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  517. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  518. INFO: [USF-XSim-97] Finding global include files...

  519. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  520. INFO: [USF-XSim-2] XSim::Compile design

  521. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  522. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  523. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  524. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  525. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  526. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  527. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  528. INFO: [USF-XSim-3] XSim::Elaborate design

  529. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  530. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  531. Vivado Simulator v2021.2

  532. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  533. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  534. Using 2 slave threads.

  535. Starting static elaboration

  536. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  537. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  538. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  539. Completed static elaboration

  540. Starting simulation data flow analysis

  541. Completed simulation data flow analysis

  542. Time Resolution for simulation is 1ps

  543. Compiling package std.standard

  544. Compiling package std.textio

  545. Compiling package ieee.std_logic_1164

  546. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  547. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  548. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  549. Built simulation snapshot pwm_test_db_behav

  550. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  551. INFO: [USF-XSim-4] XSim::Simulate design

  552. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  553. INFO: [USF-XSim-98] *** Running xsim

  554.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  555. INFO: [USF-XSim-8] Loading simulator feature

  556. Time resolution is 1 ps

  557. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  558. source pwm_test_db.tcl

  559. # set curr_wave [current_wave_config]

  560. # if { [string length $curr_wave] == 0 } {

  561. #   if { [llength [get_objects]] > 0} {

  562. #     add_wave /

  563. #     set_property needs_save false [current_wave_config]

  564. #   } else {

  565. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  566. #   }

  567. # }

  568. # run 5 s

  569. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  570. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  571. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000

  572. reset_run synth_1

  573. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  574. WARNING: [Vivado 12-1017] Problems encountered:

  575. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  576. 

  577. launch_runs synth_1 -jobs 6

  578. [Wed May 18 20:22:54 2022] Launched synth_1...

  579. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  580. close_sim

  581. INFO: [Simtcl 6-16] Simulation closed

  582. launch_simulation

  583. Command: launch_simulation 

  584. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  585. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  586. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  587. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  588. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  589. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  590. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  591. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  592. INFO: [USF-XSim-97] Finding global include files...

  593. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  594. INFO: [USF-XSim-2] XSim::Compile design

  595. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  596. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  597. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  598. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  599. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  600. INFO: [VRFC 10-3107] analyzing entity 'regler'

  601. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  602. INFO: [USF-XSim-3] XSim::Elaborate design

  603. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  604. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  605. Vivado Simulator v2021.2

  606. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  607. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  608. Using 2 slave threads.

  609. Starting static elaboration

  610. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  611. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  612. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  613. Completed static elaboration

  614. Starting simulation data flow analysis

  615. Completed simulation data flow analysis

  616. Time Resolution for simulation is 1ps

  617. Compiling package std.standard

  618. Compiling package std.textio

  619. Compiling package ieee.std_logic_1164

  620. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  621. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  622. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  623. Built simulation snapshot pwm_test_db_behav

  624. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  625. INFO: [USF-XSim-4] XSim::Simulate design

  626. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  627. INFO: [USF-XSim-98] *** Running xsim

  628.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  629. INFO: [USF-XSim-8] Loading simulator feature

  630. Time resolution is 1 ps

  631. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  632. source pwm_test_db.tcl

  633. # set curr_wave [current_wave_config]

  634. # if { [string length $curr_wave] == 0 } {

  635. #   if { [llength [get_objects]] > 0} {

  636. #     add_wave /

  637. #     set_property needs_save false [current_wave_config]

  638. #   } else {

  639. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  640. #   }

  641. # }

  642. # run 5 s

  643. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  644. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  645. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1257.480 ; gain = 0.000

  646. close_sim

  647. INFO: [Simtcl 6-16] Simulation closed

  648. launch_simulation

  649. Command: launch_simulation 

  650. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  651. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  652. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  653. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  654. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  655. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  656. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  657. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  658. INFO: [USF-XSim-97] Finding global include files...

  659. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  660. INFO: [USF-XSim-2] XSim::Compile design

  661. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  662. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  663. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  664. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  665. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  666. INFO: [USF-XSim-3] XSim::Elaborate design

  667. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  668. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  669. Vivado Simulator v2021.2

  670. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  671. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  672. Using 2 slave threads.

  673. Starting static elaboration

  674. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  675. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  676. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  677. Completed static elaboration

  678. Starting simulation data flow analysis

  679. Completed simulation data flow analysis

  680. Time Resolution for simulation is 1ps

  681. Compiling package std.standard

  682. Compiling package std.textio

  683. Compiling package ieee.std_logic_1164

  684. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  685. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  686. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  687. Built simulation snapshot pwm_test_db_behav

  688. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  689. INFO: [USF-XSim-4] XSim::Simulate design

  690. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  691. INFO: [USF-XSim-98] *** Running xsim

  692.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  693. INFO: [USF-XSim-8] Loading simulator feature

  694. Time resolution is 1 ps

  695. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  696. source pwm_test_db.tcl

  697. # set curr_wave [current_wave_config]

  698. # if { [string length $curr_wave] == 0 } {

  699. #   if { [llength [get_objects]] > 0} {

  700. #     add_wave /

  701. #     set_property needs_save false [current_wave_config]

  702. #   } else {

  703. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  704. #   }

  705. # }

  706. # run 5 s

  707. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  708. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  709. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1257.480 ; gain = 0.000

  710. reset_run synth_1

  711. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  712. WARNING: [Vivado 12-1017] Problems encountered:

  713. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  714. 

  715. launch_runs synth_1 -jobs 6

  716. [Wed May 18 20:30:29 2022] Launched synth_1...

  717. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  718. close_sim

  719. INFO: [Simtcl 6-16] Simulation closed

  720. launch_simulation

  721. Command: launch_simulation 

  722. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  723. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  724. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  725. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  726. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  727. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  728. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  729. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  730. INFO: [USF-XSim-97] Finding global include files...

  731. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  732. INFO: [USF-XSim-2] XSim::Compile design

  733. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  734. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  735. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  736. INFO: [VRFC 10-3107] analyzing entity 'regler'

  737. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  738. INFO: [USF-XSim-3] XSim::Elaborate design

  739. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  740. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  741. Vivado Simulator v2021.2

  742. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  743. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  744. Using 2 slave threads.

  745. Starting static elaboration

  746. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  747. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  748. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  749. Completed static elaboration

  750. Starting simulation data flow analysis

  751. Completed simulation data flow analysis

  752. Time Resolution for simulation is 1ps

  753. Compiling package std.standard

  754. Compiling package std.textio

  755. Compiling package ieee.std_logic_1164

  756. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  757. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  758. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  759. Built simulation snapshot pwm_test_db_behav

  760. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  761. INFO: [USF-XSim-4] XSim::Simulate design

  762. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  763. INFO: [USF-XSim-98] *** Running xsim

  764.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  765. INFO: [USF-XSim-8] Loading simulator feature

  766. Time resolution is 1 ps

  767. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  768. source pwm_test_db.tcl

  769. # set curr_wave [current_wave_config]

  770. # if { [string length $curr_wave] == 0 } {

  771. #   if { [llength [get_objects]] > 0} {

  772. #     add_wave /

  773. #     set_property needs_save false [current_wave_config]

  774. #   } else {

  775. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  776. #   }

  777. # }

  778. # run 5 s

  779. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  780. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  781. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1295.145 ; gain = 20.746

  782. close_sim

  783. INFO: [Simtcl 6-16] Simulation closed

  784. launch_simulation

  785. Command: launch_simulation 

  786. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  787. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  788. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  789. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  790. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  791. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  792. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  793. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  794. INFO: [USF-XSim-97] Finding global include files...

  795. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  796. INFO: [USF-XSim-2] XSim::Compile design

  797. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  798. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  799. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  800. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  801. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  802. INFO: [USF-XSim-3] XSim::Elaborate design

  803. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  804. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  805. Vivado Simulator v2021.2

  806. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  807. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  808. Using 2 slave threads.

  809. Starting static elaboration

  810. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  811. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  812. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  813. Completed static elaboration

  814. Starting simulation data flow analysis

  815. Completed simulation data flow analysis

  816. Time Resolution for simulation is 1ps

  817. Compiling package std.standard

  818. Compiling package std.textio

  819. Compiling package ieee.std_logic_1164

  820. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  821. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  822. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  823. Built simulation snapshot pwm_test_db_behav

  824. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  825. INFO: [USF-XSim-4] XSim::Simulate design

  826. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  827. INFO: [USF-XSim-98] *** Running xsim

  828.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  829. INFO: [USF-XSim-8] Loading simulator feature

  830. Time resolution is 1 ps

  831. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  832. source pwm_test_db.tcl

  833. # set curr_wave [current_wave_config]

  834. # if { [string length $curr_wave] == 0 } {

  835. #   if { [llength [get_objects]] > 0} {

  836. #     add_wave /

  837. #     set_property needs_save false [current_wave_config]

  838. #   } else {

  839. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  840. #   }

  841. # }

  842. # run 5 s

  843. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  844. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  845. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1295.742 ; gain = 0.598

  846. set_property -name {xsim.simulate.runtime} -value {10 s} -objects [get_filesets sim_1]

  847. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  848. close_sim

  849. INFO: [Simtcl 6-16] Simulation closed

  850. launch_simulation

  851. Command: launch_simulation 

  852. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  853. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  854. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  855. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  856. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  857. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  858. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  859. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  860. INFO: [USF-XSim-97] Finding global include files...

  861. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  862. INFO: [USF-XSim-2] XSim::Compile design

  863. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  864. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  865. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  866. INFO: [USF-XSim-3] XSim::Elaborate design

  867. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  868. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  869. Vivado Simulator v2021.2

  870. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  871. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  872. Using 2 slave threads.

  873. Starting static elaboration

  874. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  875. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  876. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  877. Completed static elaboration

  878. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  879. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  880. INFO: [USF-XSim-4] XSim::Simulate design

  881. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  882. INFO: [USF-XSim-98] *** Running xsim

  883.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  884. INFO: [USF-XSim-8] Loading simulator feature

  885. Time resolution is 1 ps

  886. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  887. source pwm_test_db.tcl

  888. # set curr_wave [current_wave_config]

  889. # if { [string length $curr_wave] == 0 } {

  890. #   if { [llength [get_objects]] > 0} {

  891. #     add_wave /

  892. #     set_property needs_save false [current_wave_config]

  893. #   } else {

  894. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  895. #   }

  896. # }

  897. # run 10 s

  898. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  899. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  900. launch_simulation: Time (s): cpu = 00:00:08 ; elapsed = 00:00:10 . Memory (MB): peak = 1320.121 ; gain = 0.000

  901. close_sim

  902. INFO: [Simtcl 6-16] Simulation closed

  903. launch_simulation

  904. Command: launch_simulation 

  905. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  906. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  907. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  908. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  909. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  910. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  911. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  912. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  913. INFO: [USF-XSim-97] Finding global include files...

  914. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  915. INFO: [USF-XSim-2] XSim::Compile design

  916. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  917. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  918. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  919. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  920. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  921. INFO: [VRFC 10-3107] analyzing entity 'regler'

  922. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  923. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  924. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  925. INFO: [USF-XSim-3] XSim::Elaborate design

  926. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  927. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  928. Vivado Simulator v2021.2

  929. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  930. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  931. Using 2 slave threads.

  932. Starting static elaboration

  933. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  934. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  935. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:65]

  936. Completed static elaboration

  937. Starting simulation data flow analysis

  938. Completed simulation data flow analysis

  939. Time Resolution for simulation is 1ps

  940. Compiling package std.standard

  941. Compiling package std.textio

  942. Compiling package ieee.std_logic_1164

  943. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  944. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  945. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  946. Built simulation snapshot pwm_test_db_behav

  947. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  948. INFO: [USF-XSim-4] XSim::Simulate design

  949. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  950. INFO: [USF-XSim-98] *** Running xsim

  951.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  952. INFO: [USF-XSim-8] Loading simulator feature

  953. Time resolution is 1 ps

  954. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  955. source pwm_test_db.tcl

  956. # set curr_wave [current_wave_config]

  957. # if { [string length $curr_wave] == 0 } {

  958. #   if { [llength [get_objects]] > 0} {

  959. #     add_wave /

  960. #     set_property needs_save false [current_wave_config]

  961. #   } else {

  962. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  963. #   }

  964. # }

  965. # run 10 s

  966. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  967. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  968. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1381.312 ; gain = 25.016

  969. reset_run synth_1

  970. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  971. WARNING: [Vivado 12-1017] Problems encountered:

  972. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  973. 

  974. launch_runs synth_1 -jobs 6

  975. [Wed May 18 20:50:45 2022] Launched synth_1...

  976. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  977. close_sim

  978. INFO: [Simtcl 6-16] Simulation closed

  979. launch_simulation

  980. Command: launch_simulation 

  981. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  982. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  983. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  984. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  985. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  986. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  987. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  988. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  989. INFO: [USF-XSim-97] Finding global include files...

  990. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  991. INFO: [USF-XSim-2] XSim::Compile design

  992. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  993. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  994. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  995. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  996. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  997. INFO: [VRFC 10-3107] analyzing entity 'regler'

  998. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  999. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1000. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1001. INFO: [USF-XSim-3] XSim::Elaborate design

  1002. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1003. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1004. Vivado Simulator v2021.2

  1005. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1006. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1007. Using 2 slave threads.

  1008. Starting static elaboration

  1009. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1010. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1011. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1012. Completed static elaboration

  1013. Starting simulation data flow analysis

  1014. Completed simulation data flow analysis

  1015. Time Resolution for simulation is 1ps

  1016. Compiling package std.standard

  1017. Compiling package std.textio

  1018. Compiling package ieee.std_logic_1164

  1019. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1020. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1021. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1022. Built simulation snapshot pwm_test_db_behav

  1023. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  1024. INFO: [USF-XSim-4] XSim::Simulate design

  1025. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1026. INFO: [USF-XSim-98] *** Running xsim

  1027.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1028. INFO: [USF-XSim-8] Loading simulator feature

  1029. Time resolution is 1 ps

  1030. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1031. source pwm_test_db.tcl

  1032. # set curr_wave [current_wave_config]

  1033. # if { [string length $curr_wave] == 0 } {

  1034. #   if { [llength [get_objects]] > 0} {

  1035. #     add_wave /

  1036. #     set_property needs_save false [current_wave_config]

  1037. #   } else {

  1038. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1039. #   }

  1040. # }

  1041. # run 10 s

  1042. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1043. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1044. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:10 . Memory (MB): peak = 1388.887 ; gain = 7.539

  1045. reset_run synth_1

  1046. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  1047. WARNING: [Vivado 12-1017] Problems encountered:

  1048. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  1049. 

  1050. launch_runs synth_1 -jobs 6

  1051. [Wed May 18 21:06:16 2022] Launched synth_1...

  1052. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  1053. close_sim

  1054. INFO: [Simtcl 6-16] Simulation closed

  1055. launch_simulation

  1056. Command: launch_simulation 

  1057. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1058. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1059. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1060. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1061. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1062. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1063. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1064. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1065. INFO: [USF-XSim-97] Finding global include files...

  1066. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1067. INFO: [USF-XSim-2] XSim::Compile design

  1068. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1069. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1070. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  1071. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  1072. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1073. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1074. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1075. INFO: [USF-XSim-3] XSim::Elaborate design

  1076. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1077. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1078. Vivado Simulator v2021.2

  1079. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1080. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1081. Using 2 slave threads.

  1082. Starting static elaboration

  1083. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1084. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1085. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1086. Completed static elaboration

  1087. Starting simulation data flow analysis

  1088. Completed simulation data flow analysis

  1089. Time Resolution for simulation is 1ps

  1090. Compiling package std.standard

  1091. Compiling package std.textio

  1092. Compiling package ieee.std_logic_1164

  1093. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1094. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1095. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1096. Built simulation snapshot pwm_test_db_behav

  1097. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1098. INFO: [USF-XSim-4] XSim::Simulate design

  1099. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1100. INFO: [USF-XSim-98] *** Running xsim

  1101.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1102. INFO: [USF-XSim-8] Loading simulator feature

  1103. Time resolution is 1 ps

  1104. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1105. source pwm_test_db.tcl

  1106. # set curr_wave [current_wave_config]

  1107. # if { [string length $curr_wave] == 0 } {

  1108. #   if { [llength [get_objects]] > 0} {

  1109. #     add_wave /

  1110. #     set_property needs_save false [current_wave_config]

  1111. #   } else {

  1112. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1113. #   }

  1114. # }

  1115. # run 10 s

  1116. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1117. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1118. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:08 . Memory (MB): peak = 1391.688 ; gain = 2.801

  1119. close_sim

  1120. INFO: [Simtcl 6-16] Simulation closed

  1121. launch_simulation

  1122. Command: launch_simulation 

  1123. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1124. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1125. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1126. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1127. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1128. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1129. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1130. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1131. INFO: [USF-XSim-97] Finding global include files...

  1132. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1133. INFO: [USF-XSim-2] XSim::Compile design

  1134. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1135. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1136. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1137. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1138. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1139. INFO: [USF-XSim-3] XSim::Elaborate design

  1140. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1141. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1142. Vivado Simulator v2021.2

  1143. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1144. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1145. Using 2 slave threads.

  1146. Starting static elaboration

  1147. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1148. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1149. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1150. Completed static elaboration

  1151. Starting simulation data flow analysis

  1152. Completed simulation data flow analysis

  1153. Time Resolution for simulation is 1ps

  1154. Compiling package std.standard

  1155. Compiling package std.textio

  1156. Compiling package ieee.std_logic_1164

  1157. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1158. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1159. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1160. Built simulation snapshot pwm_test_db_behav

  1161. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1162. INFO: [USF-XSim-4] XSim::Simulate design

  1163. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1164. INFO: [USF-XSim-98] *** Running xsim

  1165.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1166. INFO: [USF-XSim-8] Loading simulator feature

  1167. Time resolution is 1 ps

  1168. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1169. source pwm_test_db.tcl

  1170. # set curr_wave [current_wave_config]

  1171. # if { [string length $curr_wave] == 0 } {

  1172. #   if { [llength [get_objects]] > 0} {

  1173. #     add_wave /

  1174. #     set_property needs_save false [current_wave_config]

  1175. #   } else {

  1176. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1177. #   }

  1178. # }

  1179. # run 10 s

  1180. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1181. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1182. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1391.777 ; gain = 0.090

  1183. close_sim

  1184. INFO: [Simtcl 6-16] Simulation closed

  1185. launch_simulation

  1186. Command: launch_simulation 

  1187. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1188. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1189. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1190. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1191. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1192. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1193. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1194. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1195. INFO: [USF-XSim-97] Finding global include files...

  1196. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1197. INFO: [USF-XSim-2] XSim::Compile design

  1198. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1199. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1200. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1201. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1202. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1203. INFO: [USF-XSim-3] XSim::Elaborate design

  1204. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1205. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1206. Vivado Simulator v2021.2

  1207. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1208. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1209. Using 2 slave threads.

  1210. Starting static elaboration

  1211. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1212. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1213. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1214. Completed static elaboration

  1215. Starting simulation data flow analysis

  1216. Completed simulation data flow analysis

  1217. Time Resolution for simulation is 1ps

  1218. Compiling package std.standard

  1219. Compiling package std.textio

  1220. Compiling package ieee.std_logic_1164

  1221. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1222. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1223. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1224. Built simulation snapshot pwm_test_db_behav

  1225. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1226. INFO: [USF-XSim-4] XSim::Simulate design

  1227. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1228. INFO: [USF-XSim-98] *** Running xsim

  1229.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1230. INFO: [USF-XSim-8] Loading simulator feature

  1231. Time resolution is 1 ps

  1232. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1233. source pwm_test_db.tcl

  1234. # set curr_wave [current_wave_config]

  1235. # if { [string length $curr_wave] == 0 } {

  1236. #   if { [llength [get_objects]] > 0} {

  1237. #     add_wave /

  1238. #     set_property needs_save false [current_wave_config]

  1239. #   } else {

  1240. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1241. #   }

  1242. # }

  1243. # run 10 s

  1244. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1245. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1246. launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:09 . Memory (MB): peak = 1392.230 ; gain = 0.430

  1247. close_sim

  1248. INFO: [Simtcl 6-16] Simulation closed

  1249. launch_simulation

  1250. Command: launch_simulation 

  1251. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1252. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1253. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1254. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1255. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1256. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1257. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1258. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1259. INFO: [USF-XSim-97] Finding global include files...

  1260. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1261. INFO: [USF-XSim-2] XSim::Compile design

  1262. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1263. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1264. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1265. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1266. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  1267. INFO: [USF-XSim-3] XSim::Elaborate design

  1268. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1269. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1270. Vivado Simulator v2021.2

  1271. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1272. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1273. Using 2 slave threads.

  1274. Starting static elaboration

  1275. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1276. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1277. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1278. Completed static elaboration

  1279. Starting simulation data flow analysis

  1280. Completed simulation data flow analysis

  1281. Time Resolution for simulation is 1ps

  1282. Compiling package std.standard

  1283. Compiling package std.textio

  1284. Compiling package ieee.std_logic_1164

  1285. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1286. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1287. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1288. Built simulation snapshot pwm_test_db_behav

  1289. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  1290. INFO: [USF-XSim-4] XSim::Simulate design

  1291. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1292. INFO: [USF-XSim-98] *** Running xsim

  1293.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1294. INFO: [USF-XSim-8] Loading simulator feature

  1295. Time resolution is 1 ps

  1296. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1297. source pwm_test_db.tcl

  1298. # set curr_wave [current_wave_config]

  1299. # if { [string length $curr_wave] == 0 } {

  1300. #   if { [llength [get_objects]] > 0} {

  1301. #     add_wave /

  1302. #     set_property needs_save false [current_wave_config]

  1303. #   } else {

  1304. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1305. #   }

  1306. # }

  1307. # run 10 s

  1308. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1309. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1310. launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1393.195 ; gain = 0.777

  1311. close_sim

  1312. INFO: [Simtcl 6-16] Simulation closed

  1313. launch_simulation

  1314. Command: launch_simulation 

  1315. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1316. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1317. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1318. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1319. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1320. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1321. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1322. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1323. INFO: [USF-XSim-97] Finding global include files...

  1324. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1325. INFO: [USF-XSim-2] XSim::Compile design

  1326. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1327. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1328. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1329. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1330. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1331. INFO: [USF-XSim-3] XSim::Elaborate design

  1332. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1333. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1334. Vivado Simulator v2021.2

  1335. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1336. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1337. Using 2 slave threads.

  1338. Starting static elaboration

  1339. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1340. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1341. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1342. Completed static elaboration

  1343. Starting simulation data flow analysis

  1344. Completed simulation data flow analysis

  1345. Time Resolution for simulation is 1ps

  1346. Compiling package std.standard

  1347. Compiling package std.textio

  1348. Compiling package ieee.std_logic_1164

  1349. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1350. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1351. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1352. Built simulation snapshot pwm_test_db_behav

  1353. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1354. INFO: [USF-XSim-4] XSim::Simulate design

  1355. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1356. INFO: [USF-XSim-98] *** Running xsim

  1357.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1358. INFO: [USF-XSim-8] Loading simulator feature

  1359. Time resolution is 1 ps

  1360. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1361. source pwm_test_db.tcl

  1362. # set curr_wave [current_wave_config]

  1363. # if { [string length $curr_wave] == 0 } {

  1364. #   if { [llength [get_objects]] > 0} {

  1365. #     add_wave /

  1366. #     set_property needs_save false [current_wave_config]

  1367. #   } else {

  1368. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1369. #   }

  1370. # }

  1371. # run 10 s

  1372. ERROR: File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd Line: 118 : Division by zero is not allowed.

  1373. Time: 986 us  Iteration: 1  Process: /pwm_test_db/uut_regler/line__91

  1374.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd

  1375. 

  1376. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:118

  1377. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1378. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1379. launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1393.648 ; gain = 0.453

  1380. reset_run synth_1

  1381. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  1382. WARNING: [Vivado 12-1017] Problems encountered:

  1383. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  1384. 

  1385. launch_runs synth_1 -jobs 6

  1386. [Wed May 18 21:16:15 2022] Launched synth_1...

  1387. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  1388. close_sim

  1389. INFO: [Simtcl 6-16] Simulation closed

  1390. launch_simulation

  1391. Command: launch_simulation 

  1392. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1393. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1394. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1395. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1396. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1397. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1398. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1399. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1400. INFO: [USF-XSim-97] Finding global include files...

  1401. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1402. INFO: [USF-XSim-2] XSim::Compile design

  1403. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1404. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1405. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  1406. INFO: [VRFC 10-3107] analyzing entity 'regler'

  1407. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1408. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1409. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1410. INFO: [USF-XSim-3] XSim::Elaborate design

  1411. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1412. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1413. Vivado Simulator v2021.2

  1414. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1415. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1416. Using 2 slave threads.

  1417. Starting static elaboration

  1418. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1419. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1420. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1421. Completed static elaboration

  1422. Starting simulation data flow analysis

  1423. Completed simulation data flow analysis

  1424. Time Resolution for simulation is 1ps

  1425. Compiling package std.standard

  1426. Compiling package std.textio

  1427. Compiling package ieee.std_logic_1164

  1428. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1429. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1430. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1431. Built simulation snapshot pwm_test_db_behav

  1432. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1433. INFO: [USF-XSim-4] XSim::Simulate design

  1434. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1435. INFO: [USF-XSim-98] *** Running xsim

  1436.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1437. INFO: [USF-XSim-8] Loading simulator feature

  1438. Time resolution is 1 ps

  1439. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1440. source pwm_test_db.tcl

  1441. # set curr_wave [current_wave_config]

  1442. # if { [string length $curr_wave] == 0 } {

  1443. #   if { [llength [get_objects]] > 0} {

  1444. #     add_wave /

  1445. #     set_property needs_save false [current_wave_config]

  1446. #   } else {

  1447. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1448. #   }

  1449. # }

  1450. # run 10 s

  1451. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1452. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1453. launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1394.277 ; gain = 0.629

  1454. close_sim

  1455. INFO: [Simtcl 6-16] Simulation closed

  1456. launch_simulation

  1457. Command: launch_simulation 

  1458. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1459. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1460. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1461. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1462. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1463. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1464. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1465. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1466. INFO: [USF-XSim-97] Finding global include files...

  1467. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1468. INFO: [USF-XSim-2] XSim::Compile design

  1469. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1470. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1471. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1472. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1473. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1474. INFO: [USF-XSim-3] XSim::Elaborate design

  1475. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1476. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1477. Vivado Simulator v2021.2

  1478. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1479. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1480. Using 2 slave threads.

  1481. Starting static elaboration

  1482. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1483. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1484. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1485. Completed static elaboration

  1486. Starting simulation data flow analysis

  1487. Completed simulation data flow analysis

  1488. Time Resolution for simulation is 1ps

  1489. Compiling package std.standard

  1490. Compiling package std.textio

  1491. Compiling package ieee.std_logic_1164

  1492. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1493. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1494. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1495. Built simulation snapshot pwm_test_db_behav

  1496. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1497. INFO: [USF-XSim-4] XSim::Simulate design

  1498. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1499. INFO: [USF-XSim-98] *** Running xsim

  1500.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1501. INFO: [USF-XSim-8] Loading simulator feature

  1502. Time resolution is 1 ps

  1503. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1504. source pwm_test_db.tcl

  1505. # set curr_wave [current_wave_config]

  1506. # if { [string length $curr_wave] == 0 } {

  1507. #   if { [llength [get_objects]] > 0} {

  1508. #     add_wave /

  1509. #     set_property needs_save false [current_wave_config]

  1510. #   } else {

  1511. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1512. #   }

  1513. # }

  1514. # run 10 s

  1515. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1516. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1517. launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:08 . Memory (MB): peak = 1394.953 ; gain = 0.676

  1518. reset_run synth_1

  1519. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  1520. WARNING: [Vivado 12-1017] Problems encountered:

  1521. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  1522. 

  1523. launch_runs synth_1 -jobs 6

  1524. [Wed May 18 21:23:02 2022] Launched synth_1...

  1525. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  1526. close_sim

  1527. INFO: [Simtcl 6-16] Simulation closed

  1528. launch_simulation

  1529. Command: launch_simulation 

  1530. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1531. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1532. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1533. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1534. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1535. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1536. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1537. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1538. INFO: [USF-XSim-97] Finding global include files...

  1539. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1540. INFO: [USF-XSim-2] XSim::Compile design

  1541. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1542. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1543. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  1544. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  1545. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  1546. INFO: [VRFC 10-3107] analyzing entity 'regler'

  1547. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1548. INFO: [USF-XSim-3] XSim::Elaborate design

  1549. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1550. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1551. Vivado Simulator v2021.2

  1552. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1553. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1554. Using 2 slave threads.

  1555. Starting static elaboration

  1556. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1557. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1558. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1559. Completed static elaboration

  1560. Starting simulation data flow analysis

  1561. Completed simulation data flow analysis

  1562. Time Resolution for simulation is 1ps

  1563. Compiling package std.standard

  1564. Compiling package std.textio

  1565. Compiling package ieee.std_logic_1164

  1566. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1567. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1568. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1569. Built simulation snapshot pwm_test_db_behav

  1570. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  1571. INFO: [USF-XSim-4] XSim::Simulate design

  1572. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1573. INFO: [USF-XSim-98] *** Running xsim

  1574.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1575. INFO: [USF-XSim-8] Loading simulator feature

  1576. Time resolution is 1 ps

  1577. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1578. source pwm_test_db.tcl

  1579. # set curr_wave [current_wave_config]

  1580. # if { [string length $curr_wave] == 0 } {

  1581. #   if { [llength [get_objects]] > 0} {

  1582. #     add_wave /

  1583. #     set_property needs_save false [current_wave_config]

  1584. #   } else {

  1585. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1586. #   }

  1587. # }

  1588. # run 10 s

  1589. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1590. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1591. launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1395.184 ; gain = 0.207

  1592. reset_run synth_1

  1593. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  1594. WARNING: [Vivado 12-1017] Problems encountered:

  1595. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  1596. 

  1597. close_sim

  1598. INFO: [Simtcl 6-16] Simulation closed

  1599. launch_simulation

  1600. Command: launch_simulation 

  1601. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1602. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1603. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1604. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1605. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1606. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1607. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1608. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1609. INFO: [USF-XSim-97] Finding global include files...

  1610. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1611. INFO: [USF-XSim-2] XSim::Compile design

  1612. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1613. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1614. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1615. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1616. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  1617. INFO: [USF-XSim-3] XSim::Elaborate design

  1618. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1619. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1620. Vivado Simulator v2021.2

  1621. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1622. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1623. Using 2 slave threads.

  1624. Starting static elaboration

  1625. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1626. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1627. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1628. Completed static elaboration

  1629. Starting simulation data flow analysis

  1630. Completed simulation data flow analysis

  1631. Time Resolution for simulation is 1ps

  1632. Compiling package std.standard

  1633. Compiling package std.textio

  1634. Compiling package ieee.std_logic_1164

  1635. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1636. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1637. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1638. Built simulation snapshot pwm_test_db_behav

  1639. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  1640. INFO: [USF-XSim-4] XSim::Simulate design

  1641. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1642. INFO: [USF-XSim-98] *** Running xsim

  1643.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1644. INFO: [USF-XSim-8] Loading simulator feature

  1645. Time resolution is 1 ps

  1646. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1647. source pwm_test_db.tcl

  1648. # set curr_wave [current_wave_config]

  1649. # if { [string length $curr_wave] == 0 } {

  1650. #   if { [llength [get_objects]] > 0} {

  1651. #     add_wave /

  1652. #     set_property needs_save false [current_wave_config]

  1653. #   } else {

  1654. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1655. #   }

  1656. # }

  1657. # run 10 s

  1658. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1659. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1660. launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1396.844 ; gain = 0.105

  1661. close_sim

  1662. INFO: [Simtcl 6-16] Simulation closed

  1663. launch_simulation

  1664. Command: launch_simulation 

  1665. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  1666. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  1667. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1668. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  1669. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  1670. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  1671. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1672. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  1673. INFO: [USF-XSim-97] Finding global include files...

  1674. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  1675. INFO: [USF-XSim-2] XSim::Compile design

  1676. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1677. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  1678. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  1679. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  1680. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  1681. INFO: [USF-XSim-3] XSim::Elaborate design

  1682. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1683. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  1684. Vivado Simulator v2021.2

  1685. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  1686. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  1687. Using 2 slave threads.

  1688. Starting static elaboration

  1689. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:67]

  1690. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:68]

  1691. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:69]

  1692. Completed static elaboration

  1693. Starting simulation data flow analysis

  1694. Completed simulation data flow analysis

  1695. Time Resolution for simulation is 1ps

  1696. Compiling package std.standard

  1697. Compiling package std.textio

  1698. Compiling package ieee.std_logic_1164

  1699. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  1700. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  1701. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  1702. Built simulation snapshot pwm_test_db_behav

  1703. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  1704. INFO: [USF-XSim-4] XSim::Simulate design

  1705. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  1706. INFO: [USF-XSim-98] *** Running xsim

  1707.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  1708. INFO: [USF-XSim-8] Loading simulator feature

  1709. Time resolution is 1 ps

  1710. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  1711. source pwm_test_db.tcl

  1712. # set curr_wave [current_wave_config]

  1713. # if { [string length $curr_wave] == 0 } {

  1714. #   if { [llength [get_objects]] > 0} {

  1715. #     add_wave /

  1716. #     set_property needs_save false [current_wave_config]

  1717. #   } else {

  1718. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  1719. #   }

  1720. # }

  1721. # run 10 s

  1722. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  1723. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  1724. launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1408.062 ; gain = 11.219

  1725. close_sim

  1726. INFO: [Simtcl 6-16] Simulation closed

  1727. exit

  1728. INFO: [Common 17-206] Exiting Vivado at Wed May 18 21:41:31 2022...