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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log

vivado_5492.backup.log 90KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Fri May 13 11:33:33 2022

  6. # Process ID: 5492

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

  15. INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

  16. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'

  17. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  18. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  19. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  20. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  21. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  22. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available

  23. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available

  24. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available

  25. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  26. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  27. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  28. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  29. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available

  30. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  31. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  32. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  33. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available

  34. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available

  35. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available

  36. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available

  37. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available

  38. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  39. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  40. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available

  41. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available

  42. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  43. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  44. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  45. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  46. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  47. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  48. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  49. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available

  50. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  51. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  52. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  53. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available

  54. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available

  55. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  56. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  57. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  58. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  59. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  60. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available

  61. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available

  62. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.

  63. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.

  64. Scanning sources...

  65. Finished scanning sources

  66. INFO: [IP_Flow 19-234] Refreshing IP repositories

  67. INFO: [IP_Flow 19-1704] No user IP repositories specified

  68. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.

  69. open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000

  70. update_compile_order -fileset sources_1

  71. reset_run synth_1

  72. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  73. launch_runs synth_1 -jobs 6

  74. [Fri May 13 11:34:46 2022] Launched synth_1...

  75. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  76. launch_runs impl_1 -jobs 6

  77. [Fri May 13 11:36:03 2022] Launched impl_1...

  78. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log

  79. close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ]

  80. add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  81. update_compile_order -fileset sources_1

  82. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}

  83. Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...

  84. INFO: [Common 17-41] Interrupt caught. Command should exit soon.

  85. INFO: [Common 17-344] 'source' was cancelled

  86. 1

  87. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  88.  - 

  89.     while executing

  90. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  91. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  92.  - 

  93.     while executing

  94. "source init.tcl"

  95. 1

  96. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  97.  - 

  98.     while executing

  99. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  100. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  101.  - 

  102.     while executing

  103. "source init.tcl"

  104. 1

  105. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  106.  - 

  107.     while executing

  108. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  109. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  110.  - 

  111.     while executing

  112. "source init.tcl"

  113. 1

  114. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  115.  - 

  116.     while executing

  117. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  118. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  119.  - 

  120.     while executing

  121. "source init.tcl"

  122. 1

  123. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  124.  - 

  125.     while executing

  126. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  127. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  128.  - 

  129.     while executing

  130. "source init.tcl"

  131. 1

  132. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  133.  - 

  134.     while executing

  135. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  136. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  137.  - 

  138.     while executing

  139. "source init.tcl"

  140. 1

  141. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  142.  - 

  143.     while executing

  144. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  145. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  146.  - 

  147.     while executing

  148. "source init.tcl"

  149. 1

  150. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  151.  - 

  152.     while executing

  153. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  154. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  155.  - 

  156.     while executing

  157. "source init.tcl"

  158. 1

  159. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  160.  - 

  161.     while executing

  162. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  163. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  164.  - 

  165.     while executing

  166. "source init.tcl"

  167. 1

  168. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  169.  - 

  170.     while executing

  171. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  172. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  173.  - 

  174.     while executing

  175. "source init.tcl"

  176. 1

  177. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  178.  - 

  179.     while executing

  180. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  181. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  182.  - 

  183.     while executing

  184. "source init.tcl"

  185. 1

  186. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  187.  - 

  188.     while executing

  189. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  190. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  191.  - 

  192.     while executing

  193. "source init.tcl"

  194. 1

  195. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  196.  - 

  197.     while executing

  198. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  199. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  200.  - 

  201.     while executing

  202. "source init.tcl"

  203. 1

  204. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  205.  - 

  206.     while executing

  207. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  208. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  209.  - 

  210.     while executing

  211. "source init.tcl"

  212. 1

  213. ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]

  214.  - 

  215.     while executing

  216. "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]"

  217. ERROR: [Ip 78-89] Error in evaluating command source init.tcl

  218.  - 

  219.     while executing

  220. "source init.tcl"

  221. 1

  222. INFO: [BD 41-1808] Open Block Design has been cancelled.

  223. INFO: [Common 17-344] 'open_bd_design' was cancelled

  224. import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl}

  225. update_compile_order -fileset sources_1

  226. set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]

  227. set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl]

  228. set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]

  229. set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl]

  230. set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]

  231. set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl]

  232. set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]

  233. set_property library ieee_proposed [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl]

  234. reset_run synth_1

  235. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  236. launch_runs synth_1 -jobs 6

  237. [Fri May 13 12:17:21 2022] Launched synth_1...

  238. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  239. launch_runs impl_1 -jobs 6

  240. [Fri May 13 12:18:35 2022] Launched impl_1...

  241. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log

  242. open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd}

  243. Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>...

  244. Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>

  245. reset_run synth_1

  246. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  247. launch_runs synth_1 -jobs 6

  248. [Fri May 13 12:28:24 2022] Launched synth_1...

  249. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  250. launch_simulation

  251. Command: launch_simulation 

  252. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  253. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  254. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  255. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  256. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  257. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  258. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  259. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  260. INFO: [USF-XSim-97] Finding global include files...

  261. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  262. INFO: [USF-XSim-2] XSim::Compile design

  263. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  264. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  265. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  266. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  267. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  268. INFO: [VRFC 10-3107] analyzing entity 'regler'

  269. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed

  270. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed

  271. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed

  272. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed

  273. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib

  274. INFO: [VRFC 10-3107] analyzing entity 'wendeTangente'

  275. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  276. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  277. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  278. INFO: [USF-XSim-3] XSim::Elaborate design

  279. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  280. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  281. Vivado Simulator v2021.2

  282. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  283. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  284. Using 2 slave threads.

  285. Starting static elaboration

  286. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  287. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  288. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  289. Completed static elaboration

  290. Starting simulation data flow analysis

  291. ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

  292. Printing stacktrace...

  293. 

  294. [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]

  295. [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]

  296. [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]

  297. [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]

  298. [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]

  299. [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443]

  300. [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088]

  301. [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]

  302. [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]

  303. [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]

  304. [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]

  305. [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]

  306. [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]

  307. [13]  [0x7ff65f3a24cf]

  308. [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]

  309. [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]

  310. [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]

  311. [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]

  312. 

  313. Done

  314. INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds

  315. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  316. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  317. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  318. launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000

  319. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  320. launch_simulation

  321. Command: launch_simulation 

  322. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  323. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  324. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  325. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  326. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  327. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  328. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  329. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  330. INFO: [USF-XSim-97] Finding global include files...

  331. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  332. INFO: [USF-XSim-2] XSim::Compile design

  333. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  334. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  335. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  336. INFO: [USF-XSim-3] XSim::Elaborate design

  337. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  338. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  339. Vivado Simulator v2021.2

  340. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  341. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  342. Using 2 slave threads.

  343. Starting static elaboration

  344. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  345. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  346. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  347. Completed static elaboration

  348. Starting simulation data flow analysis

  349. ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

  350. Printing stacktrace...

  351. 

  352. [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]

  353. [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]

  354. [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]

  355. [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]

  356. [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]

  357. [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443]

  358. [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088]

  359. [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]

  360. [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]

  361. [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]

  362. [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]

  363. [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]

  364. [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]

  365. [13]  [0x7ff65f3a24cf]

  366. [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]

  367. [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]

  368. [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]

  369. [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]

  370. 

  371. Done

  372. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  373. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  374. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  375. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  376. launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000

  377. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  378. set_property file_type {VHDL 2008} [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]

  379. launch_simulation

  380. Command: launch_simulation 

  381. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  382. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  383. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  384. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  385. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  386. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  387. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  388. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  389. INFO: [USF-XSim-97] Finding global include files...

  390. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  391. INFO: [USF-XSim-2] XSim::Compile design

  392. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  393. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  394. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  395. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  396. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  397. INFO: [USF-XSim-3] XSim::Elaborate design

  398. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  399. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  400. Vivado Simulator v2021.2

  401. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  402. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  403. Using 2 slave threads.

  404. Starting static elaboration

  405. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  406. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  407. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  408. Completed static elaboration

  409. Starting simulation data flow analysis

  410. Completed simulation data flow analysis

  411. Time Resolution for simulation is 1ps

  412. Compiling package std.standard

  413. Compiling package std.textio

  414. Compiling package ieee.std_logic_1164

  415. Compiling package ieee.numeric_std

  416. Compiling package ieee.fixed_float_types

  417. Compiling package ieee.fixed_pkg

  418. Compiling package ieee.math_real

  419. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  420. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  421. Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]

  422. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  423. Built simulation snapshot pwm_test_db_behav

  424. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  425. INFO: [USF-XSim-4] XSim::Simulate design

  426. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  427. INFO: [USF-XSim-98] *** Running xsim

  428.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  429. INFO: [USF-XSim-8] Loading simulator feature

  430. Time resolution is 1 ps

  431. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  432. source pwm_test_db.tcl

  433. # set curr_wave [current_wave_config]

  434. # if { [string length $curr_wave] == 0 } {

  435. #   if { [llength [get_objects]] > 0} {

  436. #     add_wave /

  437. #     set_property needs_save false [current_wave_config]

  438. #   } else {

  439. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  440. #   }

  441. # }

  442. # run 5 s

  443. ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements

  444. Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51

  445.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  446. 

  447. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55

  448. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  449. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  450. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000

  451. current_wave_config {pwm_test_db_func_synth.wcfg}

  452. pwm_test_db_func_synth.wcfg

  453. add_wave {{/pwm_test_db/uutWendeTangente/a}} 

  454. current_wave_config {pwm_test_db_func_synth.wcfg}

  455. pwm_test_db_func_synth.wcfg

  456. add_wave {{/pwm_test_db/uutWendeTangente/b}} 

  457. current_wave_config {pwm_test_db_func_synth.wcfg}

  458. pwm_test_db_func_synth.wcfg

  459. add_wave {{/pwm_test_db/uutWendeTangente/c}} 

  460. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  461. close_sim

  462. INFO: [Simtcl 6-16] Simulation closed

  463. launch_simulation

  464. Command: launch_simulation 

  465. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  466. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  467. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  468. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  469. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  470. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  471. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  472. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  473. INFO: [USF-XSim-97] Finding global include files...

  474. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  475. INFO: [USF-XSim-2] XSim::Compile design

  476. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  477. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  478. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  479. INFO: [USF-XSim-3] XSim::Elaborate design

  480. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  481. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  482. Vivado Simulator v2021.2

  483. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  484. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  485. Using 2 slave threads.

  486. Starting static elaboration

  487. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  488. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  489. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  490. Completed static elaboration

  491. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  492. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  493. INFO: [USF-XSim-4] XSim::Simulate design

  494. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  495. INFO: [USF-XSim-98] *** Running xsim

  496.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  497. INFO: [USF-XSim-8] Loading simulator feature

  498. Time resolution is 1 ps

  499. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  500. source pwm_test_db.tcl

  501. # set curr_wave [current_wave_config]

  502. # if { [string length $curr_wave] == 0 } {

  503. #   if { [llength [get_objects]] > 0} {

  504. #     add_wave /

  505. #     set_property needs_save false [current_wave_config]

  506. #   } else {

  507. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  508. #   }

  509. # }

  510. # run 5 s

  511. ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements

  512. Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51

  513.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  514. 

  515. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55

  516. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  517. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  518. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000

  519. add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55

  520. remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55

  521. close_sim

  522. INFO: [Simtcl 6-16] Simulation closed

  523. launch_simulation

  524. Command: launch_simulation 

  525. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  526. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  527. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  528. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  529. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  530. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  531. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  532. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  533. INFO: [USF-XSim-97] Finding global include files...

  534. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  535. INFO: [USF-XSim-2] XSim::Compile design

  536. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  537. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  538. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  539. INFO: [USF-XSim-3] XSim::Elaborate design

  540. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  541. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  542. Vivado Simulator v2021.2

  543. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  544. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  545. Using 2 slave threads.

  546. Starting static elaboration

  547. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  548. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  549. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  550. Completed static elaboration

  551. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  552. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  553. INFO: [USF-XSim-4] XSim::Simulate design

  554. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  555. INFO: [USF-XSim-98] *** Running xsim

  556.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  557. INFO: [USF-XSim-8] Loading simulator feature

  558. Time resolution is 1 ps

  559. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  560. source pwm_test_db.tcl

  561. # set curr_wave [current_wave_config]

  562. # if { [string length $curr_wave] == 0 } {

  563. #   if { [llength [get_objects]] > 0} {

  564. #     add_wave /

  565. #     set_property needs_save false [current_wave_config]

  566. #   } else {

  567. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  568. #   }

  569. # }

  570. # run 5 s

  571. ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements

  572. Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51

  573.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  574. 

  575. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55

  576. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  577. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  578. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000

  579. close_sim

  580. INFO: [Simtcl 6-16] Simulation closed

  581. launch_simulation

  582. Command: launch_simulation 

  583. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  584. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  585. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  586. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  587. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  588. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  589. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  590. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  591. INFO: [USF-XSim-97] Finding global include files...

  592. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  593. INFO: [USF-XSim-2] XSim::Compile design

  594. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  595. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  596. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  597. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  598. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  599. INFO: [USF-XSim-3] XSim::Elaborate design

  600. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  601. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  602. Vivado Simulator v2021.2

  603. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  604. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  605. Using 2 slave threads.

  606. Starting static elaboration

  607. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  608. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  609. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  610. Completed static elaboration

  611. Starting simulation data flow analysis

  612. Completed simulation data flow analysis

  613. Time Resolution for simulation is 1ps

  614. Compiling package std.standard

  615. Compiling package std.textio

  616. Compiling package ieee.std_logic_1164

  617. Compiling package ieee.numeric_std

  618. Compiling package ieee.fixed_float_types

  619. Compiling package ieee.fixed_pkg

  620. Compiling package ieee.math_real

  621. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  622. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  623. Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]

  624. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  625. Built simulation snapshot pwm_test_db_behav

  626. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  627. INFO: [USF-XSim-4] XSim::Simulate design

  628. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  629. INFO: [USF-XSim-98] *** Running xsim

  630.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  631. INFO: [USF-XSim-8] Loading simulator feature

  632. Time resolution is 1 ps

  633. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  634. source pwm_test_db.tcl

  635. # set curr_wave [current_wave_config]

  636. # if { [string length $curr_wave] == 0 } {

  637. #   if { [llength [get_objects]] > 0} {

  638. #     add_wave /

  639. #     set_property needs_save false [current_wave_config]

  640. #   } else {

  641. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  642. #   }

  643. # }

  644. # run 5 s

  645. ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements

  646. Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51

  647.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  648. 

  649. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55

  650. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  651. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  652. launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000

  653. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  654. reset_run synth_1

  655. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  656. WARNING: [Vivado 12-1017] Problems encountered:

  657. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  658. 

  659. launch_runs synth_1 -jobs 6

  660. [Fri May 13 12:52:54 2022] Launched synth_1...

  661. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  662. close_sim

  663. INFO: [Simtcl 6-16] Simulation closed

  664. launch_simulation

  665. Command: launch_simulation 

  666. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  667. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  668. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  669. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  670. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  671. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  672. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  673. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  674. INFO: [USF-XSim-97] Finding global include files...

  675. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  676. INFO: [USF-XSim-2] XSim::Compile design

  677. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  678. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  679. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  680. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  681. ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46]

  682. ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53]

  683. ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65]

  684. ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66]

  685. ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72]

  686. ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83]

  687. ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90]

  688. ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102]

  689. ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116]

  690. ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117]

  691. ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]

  692. ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114]

  693. ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122]

  694. ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]

  695. ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121]

  696. ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126]

  697. ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43]

  698. INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors

  699. INFO: [USF-XSim-69] 'compile' step finished in '3' seconds

  700. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'

  701. ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.

  702. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  703. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  704. launch_simulation

  705. Command: launch_simulation 

  706. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  707. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  708. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  709. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  710. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  711. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  712. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  713. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  714. INFO: [USF-XSim-97] Finding global include files...

  715. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  716. INFO: [USF-XSim-2] XSim::Compile design

  717. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  718. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  719. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  720. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  721. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  722. INFO: [USF-XSim-3] XSim::Elaborate design

  723. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  724. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  725. Vivado Simulator v2021.2

  726. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  727. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  728. Using 2 slave threads.

  729. Starting static elaboration

  730. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  731. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  732. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  733. Completed static elaboration

  734. Starting simulation data flow analysis

  735. Completed simulation data flow analysis

  736. Time Resolution for simulation is 1ps

  737. Compiling package std.standard

  738. Compiling package std.textio

  739. Compiling package ieee.std_logic_1164

  740. Compiling package ieee.numeric_std

  741. Compiling package ieee.fixed_float_types

  742. Compiling package ieee.fixed_pkg

  743. Compiling package ieee.math_real

  744. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  745. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  746. Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default]

  747. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  748. Built simulation snapshot pwm_test_db_behav

  749. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  750. INFO: [USF-XSim-4] XSim::Simulate design

  751. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  752. INFO: [USF-XSim-98] *** Running xsim

  753.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  754. INFO: [USF-XSim-8] Loading simulator feature

  755. Time resolution is 1 ps

  756. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  757. source pwm_test_db.tcl

  758. # set curr_wave [current_wave_config]

  759. # if { [string length $curr_wave] == 0 } {

  760. #   if { [llength [get_objects]] > 0} {

  761. #     add_wave /

  762. #     set_property needs_save false [current_wave_config]

  763. #   } else {

  764. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  765. #   }

  766. # }

  767. # run 5 s

  768. ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements

  769. Time: 0 ps  Iteration: 0  Process: /pwm_test_db/uutWendeTangente/line__51

  770.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd

  771. 

  772. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55

  773. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  774. INFO: [USF-XSim-97] XSim simulation ran for 5 s

  775. launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000

  776. set_property file_type VHDL [get_files  C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd]

  777. close_sim

  778. INFO: [Simtcl 6-16] Simulation closed

  779. launch_simulation

  780. Command: launch_simulation 

  781. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  782. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  783. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  784. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  785. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  786. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  787. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  788. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  789. INFO: [USF-XSim-97] Finding global include files...

  790. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  791. INFO: [USF-XSim-2] XSim::Compile design

  792. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  793. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  794. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  795. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  796. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  797. INFO: [USF-XSim-3] XSim::Elaborate design

  798. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  799. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  800. Vivado Simulator v2021.2

  801. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  802. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  803. Using 2 slave threads.

  804. Starting static elaboration

  805. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  806. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  807. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  808. Completed static elaboration

  809. Starting simulation data flow analysis

  810. ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

  811. Printing stacktrace...

  812. 

  813. [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]

  814. [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]

  815. [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]

  816. [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]

  817. [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]

  818. [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9830a6443]

  819. [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9830a9088]

  820. [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]

  821. [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]

  822. [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]

  823. [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]

  824. [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]

  825. [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]

  826. [13]  [0x7ff65f3a24cf]

  827. [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]

  828. [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]

  829. [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]

  830. [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]

  831. 

  832. Done

  833. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  834. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  835. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  836. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  837. launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000

  838. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  839. launch_simulation

  840. Command: launch_simulation 

  841. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  842. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  843. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  844. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  845. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  846. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  847. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  848. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  849. INFO: [USF-XSim-97] Finding global include files...

  850. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  851. INFO: [USF-XSim-2] XSim::Compile design

  852. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  853. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  854. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  855. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  856. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  857. INFO: [USF-XSim-3] XSim::Elaborate design

  858. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  859. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  860. Vivado Simulator v2021.2

  861. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  862. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  863. Using 2 slave threads.

  864. Starting static elaboration

  865. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62]

  866. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63]

  867. WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64]

  868. Completed static elaboration

  869. Starting simulation data flow analysis

  870. ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.

  871. Printing stacktrace...

  872. 

  873. [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe]

  874. [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d]

  875. [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc]

  876. [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132]

  877. [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda]

  878. [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fad6443]

  879. [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fad9088]

  880. [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be]

  881. [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132]

  882. [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105]

  883. [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0]

  884. [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29]

  885. [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5]

  886. [13]  [0x7ff65f3a24cf]

  887. [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457]

  888. [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce]

  889. [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c]

  890. [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0]

  891. 

  892. Done

  893. INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds

  894. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  895. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  896. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  897. launch_simulation: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000

  898. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  899. exit

  900. INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:47:14 2022...