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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_pid3672.str

vivado_pid3672.str 11KB
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  1. /*

  2. 

  3. Xilinx Vivado v2021.2 (64-bit) [Major: 2021, Minor: 2]

  4. SW Build: 3367213 on Tue Oct 19 02:48:09 MDT 2021

  5. IP Build: 3369179 on Thu Oct 21 08:25:16 MDT 2021

  6. 

  7. Process ID (PID): 3672

  8. License: Customer

  9. Mode: GUI Mode

  10. 

  11. Current time: 	Fri May 13 11:28:40 CEST 2022

  12. Time zone: 	Central European Standard Time (Europe/Berlin)

  13. 

  14. OS: Windows 10

  15. OS Version: 10.0

  16. OS Architecture: amd64

  17. Available processors (cores): 12

  18. 

  19. Screen size: 1920x1080

  20. Screen resolution (DPI): 100

  21. Available screens: 2

  22. Default font: family=Dialog,name=Dialog,style=plain,size=12

  23. Scale size: 12

  24. 

  25. Java version: 	11.0.11 64-bit

  26. Java home: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9

  27. Java executable: 	C:/Xilinx/Vivado/2021.2/tps/win64/jre11.0.11_9/bin/java.exe

  28. Java arguments: 	[-Dsun.java2d.pmoffscreen=false, -Dhttps.protocols=TLSv1,TLSv1.1,TLSv1.2, -Dsun.java2d.xrender=false, -Dsun.java2d.d3d=false, -Dsun.awt.nopixfmt=true, -Dsun.java2d.dpiaware=true, -Dsun.java2d.uiScale.enabled=false, -Xverify:none, -Dswing.aatext=true, -XX:-UsePerfData, -Djdk.map.althashing.threshold=512, -XX:StringTableSize=4072, --add-opens=java.base/java.nio=ALL-UNNAMED, --add-opens=java.desktop/sun.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.tree=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.basic=ALL-UNNAMED, --add-opens=java.desktop/javax.swing.plaf.synth=ALL-UNNAMED, --add-opens=java.desktop/com.sun.awt=ALL-UNNAMED, -XX:NewSize=60m, -XX:MaxNewSize=60m, -Xms256m, -Xmx3072m, -Xss5m]

  29. Java initial memory (-Xms): 	256 MB

  30. Java maximum memory (-Xmx):	 3 GB

  31. 

  32. 

  33. User name: 	Felix

  34. User home directory: C:/Users/Felix

  35. User working directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  36. User country: 	DE

  37. User language: 	de

  38. User locale: 	de_DE

  39. 

  40. RDI_BASEROOT: C:/Xilinx/Vivado

  41. HDI_APPROOT: C:/Xilinx/Vivado/2021.2

  42. RDI_DATADIR: C:/Xilinx/Vivado/2021.2/data

  43. RDI_BINDIR: C:/Xilinx/Vivado/2021.2/bin

  44. 

  45. Vivado preferences file: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/vivado.xml

  46. Vivado preferences directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/

  47. Vivado layouts directory: C:/Users/Felix/AppData/Roaming/Xilinx/Vivado/2021.2/data/layouts

  48. PlanAhead jar file: 	C:/Xilinx/Vivado/2021.2/lib/classes/planAhead.jar

  49. Vivado log file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  50. Vivado journal file: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou

  51. Engine tmp dir: 	C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/.Xil/Vivado-3672-DESKTOP-PAACOM8

  52. 

  53. Xilinx Environment Variables

  54. ----------------------------

  55. TWINCATSDK: C:\TwinCAT\3.1\SDK\

  56. XILINX: C:/Xilinx/Vivado/2021.2/ids_lite/ISE

  57. XILINX_DSP: C:/Xilinx/Vivado/2021.2/ids_lite/ISE

  58. XILINX_HLS: C:/Xilinx/Vitis_HLS/2021.2

  59. XILINX_PLANAHEAD: C:/Xilinx/Vivado/2021.2

  60. XILINX_VIVADO: C:/Xilinx/Vivado/2021.2

  61. XILINX_VIVADO_HLS: C:/Xilinx/Vivado/2021.2

  62. 

  63. 

  64. GUI allocated memory:	256 MB

  65. GUI max memory:		3,072 MB

  66. Engine allocated memory: 1,300 MB

  67. 

  68. Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  69. 

  70. */

  71. 

  72. // TclEventType: START_GUI

  73. // Tcl Message: start_gui 

  74. // TclEventType: PROJECT_OPEN_DIALOG

  75. // Opening Vivado Project: C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr. Version: Vivado v2021.2 

  76. // TclEventType: DEBUG_PROBE_SET_CHANGE

  77. // TclEventType: FLOW_ADDED

  78. // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 

  79. // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 

  80. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 57 MB. Current time: 5/13/22, 11:28:41 AM CEST

  81. // TclEventType: MSGMGR_MOVEMSG

  82. // TclEventType: FILE_SET_CHANGE

  83. // TclEventType: FILE_SET_NEW

  84. // TclEventType: RUN_COMPLETED

  85. // TclEventType: RUN_STATUS_CHANGE

  86. // TclEventType: RUN_CURRENT

  87. // TclEventType: PROJECT_DASHBOARD_NEW

  88. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  89. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  90. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  91. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  92. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  93. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  94. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  95. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  96. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  97. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  98. // TclEventType: PROJECT_DASHBOARD_GADGET_NEW

  99. // TclEventType: PROJECT_DASHBOARD_GADGET_CHANGE

  100. // TclEventType: PROJECT_NEW

  101. // Tcl Message: open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr 

  102. // Tcl Message: INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' 

  103. // Tcl Message: INFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' since last save. 

  104. // Tcl Message: INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. 

  105. // Tcl Message: Scanning sources... Finished scanning sources 

  106. // Tcl Message: INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified 

  107. // TclEventType: PROJECT_NEW

  108. // [GUI Memory]: 79 MB (+80353kb) [00:00:27]

  109. // [Engine Memory]: 1,300 MB (+1211828kb) [00:00:27]

  110. // WARNING: HEventQueue.dispatchEvent() is taking  7148 ms.

  111. // WARNING: HEventQueue.dispatchEvent() is taking  1355 ms.

  112. // Tcl Message: INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. 

  113. // [GUI Memory]: 107 MB (+24993kb) [00:00:34]

  114. // Tcl Message: open_project: Time (s): cpu = 00:00:42 ; elapsed = 00:00:21 . Memory (MB): peak = 1576.332 ; gain = 0.000 

  115. // Project name: Coraz7_Test; location: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim; part: xc7z010clg400-1

  116. dismissDialog("Open Project"); // bA

  117. // Tcl Message: update_compile_order -fileset sources_1 

  118. // Elapsed time: 10 seconds

  119. selectTree(PAResourceEtoH.FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE, "[, Synthesis, Run Synthesis]", 14, false); // n

  120. // Run Command: PAResourceCommand.PACommandNames_RUN_SYNTHESIS

  121. selectButton("OptionPane.button", "OK"); // JButton

  122. // TclEventType: RUN_MODIFY

  123. // TclEventType: RUN_RESET

  124. // TclEventType: RUN_STATUS_CHANGE

  125. // TclEventType: RUN_RESET

  126. // TclEventType: RUN_MODIFY

  127. // Tcl Message: reset_run synth_1 

  128. // Tcl Message: INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp 

  129. // TclEventType: FILE_SET_CHANGE

  130. selectButton(RDIResource.BaseDialog_OK, "OK"); // a

  131. dismissDialog("Launch Runs"); // f

  132. // TclEventType: RUN_LAUNCH

  133. // TclEventType: RUN_MODIFY

  134. // TclEventType: RUN_STATUS_CHANGE

  135. // Tcl Message: launch_runs synth_1 -jobs 6 

  136. // Tcl Message: [Fri May 13 11:29:15 2022] Launched synth_1... Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log 

  137. // TclEventType: RUN_STATUS_CHANGE

  138. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:29:44 AM CEST

  139. // TclEventType: RUN_COMPLETED

  140. // TclEventType: RUN_STATUS_CHANGE

  141. // TclEventType: RUN_STEP_COMPLETED

  142. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:30:15 AM CEST

  143. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:30:45 AM CEST

  144. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 62 MB. Current time: 5/13/22, 11:32:14 AM CEST

  145. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:32:45 AM CEST

  146. // HMemoryUtils.trashcanNow. Engine heap size: 1,300 MB. GUI used memory: 61 MB. Current time: 5/13/22, 11:33:15 AM CEST

  147. // Elapsed time: 245 seconds

  148. selectButton(RDIResource.ProgressDialog_BACKGROUND, "Background"); // a

  149. // 'k' command handler elapsed time: 249 seconds

  150. closeMainWindow("Coraz7_Test - [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr] - Vivado 2021.2"); // bb

  151. // HOptionPane Warning: 'A background task is running. Please wait until it completes to exit Vivado. If you choose to abort background task and exit immediately, you will lose all unsaved changes to project. (Background Task)'