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FPGA_Projekt_Regler
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Felix Stamm 1f4de14e3e Regler+Strecke Simulation läuft für Eingangswerte w > 100 Mio 2 years ago
StreckenSim_mitRegler Regler+Strecke Simulation läuft für Eingangswerte w > 100 Mio 2 years ago
.gitignore Initial commit 2 years ago
README.md Initial commit 2 years ago

README.md

FPGA_Projekt_Regler