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FPGA_Projekt_Regler
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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/htr.txt

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  1. REM

  2. REM Vivado(TM)

  3. REM htr.txt: a Vivado-generated description of how-to-repeat the

  4. REM          the basic steps of a run.  Note that runme.bat/sh needs

  5. REM          to be invoked for Vivado to track run status.

  6. REM Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  7. REM

  8. 

  9. vivado -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl