stammfe87185/FPGA_Projekt_Regler
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stammfe87185 496b16226d Umgestellt auf Singed 64 bit
2022-05-23 23:01:59 +02:00
StreckenSim_mitRegler
Umgestellt auf Singed 64 bit
2022-05-23 23:01:59 +02:00
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Initial commit
2022-05-13 09:21:45 +00:00
README.md
Initial commit
2022-05-13 09:21:45 +00:00

README.md

FPGA_Projekt_Regler

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Description
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Readme
108 MiB
Languages
VHDL 59.5%
C 13.4%
PureBasic 13%
Verilog 5.7%
Tcl 4.4%
Other 3.9%