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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds

regler.vds 26KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Mon May 23 22:58:42 2022

  6. # Process ID: 23388

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  8. # Command line: vivado.exe -log regler.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.vds

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. source regler.tcl -notrace

  14. create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066

  15. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp

  16. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis

  17. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  18. Command: synth_design -top regler -part xc7z010clg400-1

  19. Starting synth_design

  20. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  22. INFO: [Device 21-403] Loading part xc7z010clg400-1

  23. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  24. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  25. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  26. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  27. INFO: [Synth 8-7075] Helper process launched with PID 25492

  28. ---------------------------------------------------------------------------------

  29. Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000

  30. ---------------------------------------------------------------------------------

  31. INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]

  32. WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110]

  33. WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121]

  34. INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]

  35. WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load

  36. WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load

  37. WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load

  38. WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load

  39. WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load

  40. WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load

  41. WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load

  42. WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load

  43. WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load

  44. WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load

  45. ---------------------------------------------------------------------------------

  46. Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000

  47. ---------------------------------------------------------------------------------

  48. ---------------------------------------------------------------------------------

  49. Start Handling Custom Attributes

  50. ---------------------------------------------------------------------------------

  51. ---------------------------------------------------------------------------------

  52. Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000

  53. ---------------------------------------------------------------------------------

  54. ---------------------------------------------------------------------------------

  55. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000

  56. ---------------------------------------------------------------------------------

  57. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000

  58. INFO: [Project 1-570] Preparing netlist for logic optimization

  59. 

  60. Processing XDC Constraints

  61. Initializing timing engine

  62. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  63. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  64. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc].

  65. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.

  66. Completed Processing XDC Constraints

  67. 

  68. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000

  69. INFO: [Project 1-111] Unisim Transformation Summary:

  70. No Unisim elements were transformed.

  71. 

  72. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000

  73. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  74. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  75. ---------------------------------------------------------------------------------

  76. Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  77. ---------------------------------------------------------------------------------

  78. ---------------------------------------------------------------------------------

  79. Start Loading Part and Timing Information

  80. ---------------------------------------------------------------------------------

  81. Loading part: xc7z010clg400-1

  82. ---------------------------------------------------------------------------------

  83. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  84. ---------------------------------------------------------------------------------

  85. ---------------------------------------------------------------------------------

  86. Start Applying 'set_property' XDC Constraints

  87. ---------------------------------------------------------------------------------

  88. ---------------------------------------------------------------------------------

  89. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  90. ---------------------------------------------------------------------------------

  91. ---------------------------------------------------------------------------------

  92. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  93. ---------------------------------------------------------------------------------

  94. ---------------------------------------------------------------------------------

  95. Start RTL Component Statistics 

  96. ---------------------------------------------------------------------------------

  97. Detailed RTL Component Info : 

  98. +---Adders : 

  99. 	   2 Input  148 Bit       Adders := 2     

  100. 	   3 Input   64 Bit       Adders := 1     

  101. 	   2 Input   64 Bit       Adders := 1     

  102. 	   2 Input   20 Bit       Adders := 2     

  103. 	   2 Input   10 Bit       Adders := 1     

  104. +---Registers : 

  105. 	               64 Bit    Registers := 1     

  106. +---Multipliers : 

  107. 	              41x64  Multipliers := 1     

  108. 	              10x64  Multipliers := 1     

  109. +---Muxes : 

  110. 	   2 Input  148 Bit        Muxes := 2     

  111. 	   2 Input   20 Bit        Muxes := 2     

  112. 	   2 Input   10 Bit        Muxes := 1     

  113. ---------------------------------------------------------------------------------

  114. Finished RTL Component Statistics 

  115. ---------------------------------------------------------------------------------

  116. ---------------------------------------------------------------------------------

  117. Start Part Resource Summary

  118. ---------------------------------------------------------------------------------

  119. Part Resources:

  120. DSPs: 80 (col length:40)

  121. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  122. ---------------------------------------------------------------------------------

  123. Finished Part Resource Summary

  124. ---------------------------------------------------------------------------------

  125. ---------------------------------------------------------------------------------

  126. Start Cross Boundary and Area Optimization

  127. ---------------------------------------------------------------------------------

  128. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  129. DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B.

  130. DSP Report: operator I_k5 is absorbed into DSP I_k5.

  131. DSP Report: operator I_k5 is absorbed into DSP I_k5.

  132. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  133. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  134. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  135. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  136. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  137. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  138. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  139. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  140. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  141. DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.

  142. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  143. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  144. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  145. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  146. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  147. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  148. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  149. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  150. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  151. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  152. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  153. DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.

  154. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  155. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  156. DSP Report: Generating DSP u_reg1, operation Mode is: A*B.

  157. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  158. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  159. DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.

  160. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  161. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  162. DSP Report: Generating DSP u_reg1, operation Mode is: A*B.

  163. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  164. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  165. DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.

  166. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  167. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  168. WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load

  169. WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load

  170. WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load

  171. WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load

  172. WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load

  173. WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load

  174. WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load

  175. WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load

  176. WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load

  177. WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load

  178. ---------------------------------------------------------------------------------

  179. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551

  180. ---------------------------------------------------------------------------------

  181. ---------------------------------------------------------------------------------

  182. Start ROM, RAM, DSP, Shift Register and Retiming Reporting

  183. ---------------------------------------------------------------------------------

  184. 

  185. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)

  186. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  187. |Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 

  188. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  189. |regler      | (A:0xf4240)*B  | 21     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  190. |regler      | A*B            | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  191. |regler      | (PCIN>>17)+A*B | 24     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  192. |regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  193. |regler      | PCIN+A*B       | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  194. |regler      | (PCIN>>17)+A*B | 18     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  195. |regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  196. |regler      | (PCIN>>17)+A*B | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  197. |regler      | PCIN+A*B       | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  198. |regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  199. |regler      | (PCIN>>17)+A*B | 13     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  200. |regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  201. |regler      | (PCIN>>17)+A*B | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  202. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  203. 

  204. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.

  205. ---------------------------------------------------------------------------------

  206. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting

  207. ---------------------------------------------------------------------------------

  208. ---------------------------------------------------------------------------------

  209. Start Applying XDC Timing Constraints

  210. ---------------------------------------------------------------------------------

  211. ---------------------------------------------------------------------------------

  212. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941

  213. ---------------------------------------------------------------------------------

  214. ---------------------------------------------------------------------------------

  215. Start Timing Optimization

  216. ---------------------------------------------------------------------------------

  217. ---------------------------------------------------------------------------------

  218. Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406

  219. ---------------------------------------------------------------------------------

  220. ---------------------------------------------------------------------------------

  221. Start Technology Mapping

  222. ---------------------------------------------------------------------------------

  223. ---------------------------------------------------------------------------------

  224. Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914

  225. ---------------------------------------------------------------------------------

  226. ---------------------------------------------------------------------------------

  227. Start IO Insertion

  228. ---------------------------------------------------------------------------------

  229. ---------------------------------------------------------------------------------

  230. Start Flattening Before IO Insertion

  231. ---------------------------------------------------------------------------------

  232. ---------------------------------------------------------------------------------

  233. Finished Flattening Before IO Insertion

  234. ---------------------------------------------------------------------------------

  235. ---------------------------------------------------------------------------------

  236. Start Final Netlist Cleanup

  237. ---------------------------------------------------------------------------------

  238. ---------------------------------------------------------------------------------

  239. Finished Final Netlist Cleanup

  240. ---------------------------------------------------------------------------------

  241. ---------------------------------------------------------------------------------

  242. Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  243. ---------------------------------------------------------------------------------

  244. ---------------------------------------------------------------------------------

  245. Start Renaming Generated Instances

  246. ---------------------------------------------------------------------------------

  247. ---------------------------------------------------------------------------------

  248. Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  249. ---------------------------------------------------------------------------------

  250. ---------------------------------------------------------------------------------

  251. Start Rebuilding User Hierarchy

  252. ---------------------------------------------------------------------------------

  253. ---------------------------------------------------------------------------------

  254. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  255. ---------------------------------------------------------------------------------

  256. ---------------------------------------------------------------------------------

  257. Start Renaming Generated Ports

  258. ---------------------------------------------------------------------------------

  259. ---------------------------------------------------------------------------------

  260. Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  261. ---------------------------------------------------------------------------------

  262. ---------------------------------------------------------------------------------

  263. Start Handling Custom Attributes

  264. ---------------------------------------------------------------------------------

  265. ---------------------------------------------------------------------------------

  266. Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  267. ---------------------------------------------------------------------------------

  268. ---------------------------------------------------------------------------------

  269. Start Renaming Generated Nets

  270. ---------------------------------------------------------------------------------

  271. ---------------------------------------------------------------------------------

  272. Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  273. ---------------------------------------------------------------------------------

  274. ---------------------------------------------------------------------------------

  275. Start Writing Synthesis Report

  276. ---------------------------------------------------------------------------------

  277. 

  278. Report BlackBoxes: 

  279. +-+--------------+----------+

  280. | |BlackBox name |Instances |

  281. +-+--------------+----------+

  282. +-+--------------+----------+

  283. 

  284. Report Cell Usage: 

  285. +------+--------+------+

  286. |      |Cell    |Count |

  287. +------+--------+------+

  288. |1     |BUFG    |     1|

  289. |2     |CARRY4  |  1613|

  290. |3     |DSP48E1 |    13|

  291. |4     |LUT1    |   165|

  292. |5     |LUT2    |  1000|

  293. |6     |LUT3    |  2638|

  294. |7     |LUT4    |  2484|

  295. |8     |LUT5    |   799|

  296. |9     |LUT6    |  3246|

  297. |10    |FDRE    |   128|

  298. |11    |IBUF    |   159|

  299. |12    |OBUF    |    64|

  300. +------+--------+------+

  301. ---------------------------------------------------------------------------------

  302. Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  303. ---------------------------------------------------------------------------------

  304. Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.

  305. Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609

  306. Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  307. INFO: [Project 1-571] Translating synthesized netlist

  308. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000

  309. INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement

  310. INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds

  311. WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.

  312. INFO: [Project 1-570] Preparing netlist for logic optimization

  313. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  314. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000

  315. INFO: [Project 1-111] Unisim Transformation Summary:

  316. No Unisim elements were transformed.

  317. 

  318. Synth Design complete, checksum: b5ea81b7

  319. INFO: [Common 17-83] Releasing license: Synthesis

  320. 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.

  321. synth_design completed successfully

  322. synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160

  323. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.

  324. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb

  325. INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022...