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FPGA_Projekt_Regler
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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.bat

runme.bat 219B
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  1. @echo off

  2. 

  3. rem  Vivado (TM)

  4. rem  runme.bat: a Vivado-generated Script

  5. rem  Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  6. 

  7. 

  8. set HD_SDIR=%~dp0

  9. cd /d "%HD_SDIR%"

  10. cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*