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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

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  1. 

  2. *** Running vivado

  3.     with args -log regler.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source regler.tcl

  4. 

  5. 

  6. 

  7. ****** Vivado v2021.2 (64-bit)

  8.   **** SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  9.   **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  10.     ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.

  11. 

  12. source regler.tcl -notrace

  13. create_project: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 8.066

  14. Command: read_checkpoint -auto_incremental -incremental C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp

  15. INFO: [Vivado 12-5825] Read reference checkpoint from C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp for incremental synthesis

  16. INFO: [Vivado 12-7989] Please ensure there are no constraint changes

  17. Command: synth_design -top regler -part xc7z010clg400-1

  18. Starting synth_design

  19. Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010'

  20. INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010'

  21. INFO: [Device 21-403] Loading part xc7z010clg400-1

  22. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  23. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  24. INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.

  25. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes

  26. INFO: [Synth 8-7075] Helper process launched with PID 25492

  27. ---------------------------------------------------------------------------------

  28. Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1261.043 ; gain = 0.000

  29. ---------------------------------------------------------------------------------

  30. INFO: [Synth 8-638] synthesizing module 'regler' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]

  31. WARNING: [Synth 8-6014] Unused sequential element e_k_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:110]

  32. WARNING: [Synth 8-6014] Unused sequential element u_var_reg was removed.  [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:121]

  33. INFO: [Synth 8-256] done synthesizing module 'regler' (1#1) [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:48]

  34. WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load

  35. WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load

  36. WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load

  37. WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load

  38. WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load

  39. WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load

  40. WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load

  41. WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load

  42. WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load

  43. WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load

  44. ---------------------------------------------------------------------------------

  45. Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1261.043 ; gain = 0.000

  46. ---------------------------------------------------------------------------------

  47. ---------------------------------------------------------------------------------

  48. Start Handling Custom Attributes

  49. ---------------------------------------------------------------------------------

  50. ---------------------------------------------------------------------------------

  51. Finished Handling Custom Attributes : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000

  52. ---------------------------------------------------------------------------------

  53. ---------------------------------------------------------------------------------

  54. Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1261.043 ; gain = 0.000

  55. ---------------------------------------------------------------------------------

  56. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 1261.043 ; gain = 0.000

  57. INFO: [Project 1-570] Preparing netlist for logic optimization

  58. 

  59. Processing XDC Constraints

  60. Initializing timing engine

  61. Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  62. Finished Parsing XDC File [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]

  63. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/constrs_1/imports/digilent-xdc-master/Cora-Z7-10-Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/regler_propImpl.xdc].

  64. Resolution: To avoid this warning, move constraints listed in [.Xil/regler_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.

  65. Completed Processing XDC Constraints

  66. 

  67. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1273.594 ; gain = 0.000

  68. INFO: [Project 1-111] Unisim Transformation Summary:

  69. No Unisim elements were transformed.

  70. 

  71. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1273.594 ; gain = 0.000

  72. WARNING: [Designutils 20-4072] Reference run did not run incremental synthesis because the design is too small; reverting to default synthesis

  73. INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}

  74. ---------------------------------------------------------------------------------

  75. Finished Constraint Validation : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  76. ---------------------------------------------------------------------------------

  77. ---------------------------------------------------------------------------------

  78. Start Loading Part and Timing Information

  79. ---------------------------------------------------------------------------------

  80. Loading part: xc7z010clg400-1

  81. ---------------------------------------------------------------------------------

  82. Finished Loading Part and Timing Information : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  83. ---------------------------------------------------------------------------------

  84. ---------------------------------------------------------------------------------

  85. Start Applying 'set_property' XDC Constraints

  86. ---------------------------------------------------------------------------------

  87. ---------------------------------------------------------------------------------

  88. Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  89. ---------------------------------------------------------------------------------

  90. ---------------------------------------------------------------------------------

  91. Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 1273.594 ; gain = 12.551

  92. ---------------------------------------------------------------------------------

  93. ---------------------------------------------------------------------------------

  94. Start RTL Component Statistics 

  95. ---------------------------------------------------------------------------------

  96. Detailed RTL Component Info : 

  97. +---Adders : 

  98. 	   2 Input  148 Bit       Adders := 2     

  99. 	   3 Input   64 Bit       Adders := 1     

  100. 	   2 Input   64 Bit       Adders := 1     

  101. 	   2 Input   20 Bit       Adders := 2     

  102. 	   2 Input   10 Bit       Adders := 1     

  103. +---Registers : 

  104. 	               64 Bit    Registers := 1     

  105. +---Multipliers : 

  106. 	              41x64  Multipliers := 1     

  107. 	              10x64  Multipliers := 1     

  108. +---Muxes : 

  109. 	   2 Input  148 Bit        Muxes := 2     

  110. 	   2 Input   20 Bit        Muxes := 2     

  111. 	   2 Input   10 Bit        Muxes := 1     

  112. ---------------------------------------------------------------------------------

  113. Finished RTL Component Statistics 

  114. ---------------------------------------------------------------------------------

  115. ---------------------------------------------------------------------------------

  116. Start Part Resource Summary

  117. ---------------------------------------------------------------------------------

  118. Part Resources:

  119. DSPs: 80 (col length:40)

  120. BRAMs: 120 (col length: RAMB18 40 RAMB36 20)

  121. ---------------------------------------------------------------------------------

  122. Finished Part Resource Summary

  123. ---------------------------------------------------------------------------------

  124. ---------------------------------------------------------------------------------

  125. Start Cross Boundary and Area Optimization

  126. ---------------------------------------------------------------------------------

  127. WARNING: [Synth 8-7080] Parallel synthesis criteria is not met

  128. DSP Report: Generating DSP I_k5, operation Mode is: (A:0xf4240)*B.

  129. DSP Report: operator I_k5 is absorbed into DSP I_k5.

  130. DSP Report: operator I_k5 is absorbed into DSP I_k5.

  131. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  132. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  133. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  134. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  135. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  136. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  137. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  138. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  139. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  140. DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.

  141. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  142. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  143. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  144. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  145. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  146. DSP Report: Generating DSP I_k4, operation Mode is: A*B.

  147. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  148. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  149. DSP Report: Generating DSP I_k4, operation Mode is: (PCIN>>17)+A*B.

  150. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  151. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  152. DSP Report: Generating DSP I_k4, operation Mode is: PCIN+A*B.

  153. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  154. DSP Report: operator I_k4 is absorbed into DSP I_k4.

  155. DSP Report: Generating DSP u_reg1, operation Mode is: A*B.

  156. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  157. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  158. DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.

  159. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  160. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  161. DSP Report: Generating DSP u_reg1, operation Mode is: A*B.

  162. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  163. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  164. DSP Report: Generating DSP u_reg1, operation Mode is: (PCIN>>17)+A*B.

  165. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  166. DSP Report: operator u_reg1 is absorbed into DSP u_reg1.

  167. WARNING: [Synth 8-7129] Port TV[9] in module regler is either unconnected or has no load

  168. WARNING: [Synth 8-7129] Port TV[8] in module regler is either unconnected or has no load

  169. WARNING: [Synth 8-7129] Port TV[7] in module regler is either unconnected or has no load

  170. WARNING: [Synth 8-7129] Port TV[6] in module regler is either unconnected or has no load

  171. WARNING: [Synth 8-7129] Port TV[5] in module regler is either unconnected or has no load

  172. WARNING: [Synth 8-7129] Port TV[4] in module regler is either unconnected or has no load

  173. WARNING: [Synth 8-7129] Port TV[3] in module regler is either unconnected or has no load

  174. WARNING: [Synth 8-7129] Port TV[2] in module regler is either unconnected or has no load

  175. WARNING: [Synth 8-7129] Port TV[1] in module regler is either unconnected or has no load

  176. WARNING: [Synth 8-7129] Port TV[0] in module regler is either unconnected or has no load

  177. ---------------------------------------------------------------------------------

  178. Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 1273.594 ; gain = 12.551

  179. ---------------------------------------------------------------------------------

  180. ---------------------------------------------------------------------------------

  181. Start ROM, RAM, DSP, Shift Register and Retiming Reporting

  182. ---------------------------------------------------------------------------------

  183. 

  184. DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)

  185. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  186. |Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 

  187. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  188. |regler      | (A:0xf4240)*B  | 21     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  189. |regler      | A*B            | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  190. |regler      | (PCIN>>17)+A*B | 24     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  191. |regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  192. |regler      | PCIN+A*B       | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  193. |regler      | (PCIN>>17)+A*B | 18     | 13     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  194. |regler      | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  195. |regler      | (PCIN>>17)+A*B | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  196. |regler      | PCIN+A*B       | 24     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  197. |regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  198. |regler      | (PCIN>>17)+A*B | 13     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  199. |regler      | A*B            | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  200. |regler      | (PCIN>>17)+A*B | 18     | 10     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 

  201. +------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

  202. 

  203. Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.

  204. ---------------------------------------------------------------------------------

  205. Finished ROM, RAM, DSP, Shift Register and Retiming Reporting

  206. ---------------------------------------------------------------------------------

  207. ---------------------------------------------------------------------------------

  208. Start Applying XDC Timing Constraints

  209. ---------------------------------------------------------------------------------

  210. ---------------------------------------------------------------------------------

  211. Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:40 . Memory (MB): peak = 1288.984 ; gain = 27.941

  212. ---------------------------------------------------------------------------------

  213. ---------------------------------------------------------------------------------

  214. Start Timing Optimization

  215. ---------------------------------------------------------------------------------

  216. ---------------------------------------------------------------------------------

  217. Finished Timing Optimization : Time (s): cpu = 00:00:41 ; elapsed = 00:00:41 . Memory (MB): peak = 1297.449 ; gain = 36.406

  218. ---------------------------------------------------------------------------------

  219. ---------------------------------------------------------------------------------

  220. Start Technology Mapping

  221. ---------------------------------------------------------------------------------

  222. ---------------------------------------------------------------------------------

  223. Finished Technology Mapping : Time (s): cpu = 00:00:44 ; elapsed = 00:00:45 . Memory (MB): peak = 1507.957 ; gain = 246.914

  224. ---------------------------------------------------------------------------------

  225. ---------------------------------------------------------------------------------

  226. Start IO Insertion

  227. ---------------------------------------------------------------------------------

  228. ---------------------------------------------------------------------------------

  229. Start Flattening Before IO Insertion

  230. ---------------------------------------------------------------------------------

  231. ---------------------------------------------------------------------------------

  232. Finished Flattening Before IO Insertion

  233. ---------------------------------------------------------------------------------

  234. ---------------------------------------------------------------------------------

  235. Start Final Netlist Cleanup

  236. ---------------------------------------------------------------------------------

  237. ---------------------------------------------------------------------------------

  238. Finished Final Netlist Cleanup

  239. ---------------------------------------------------------------------------------

  240. ---------------------------------------------------------------------------------

  241. Finished IO Insertion : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  242. ---------------------------------------------------------------------------------

  243. ---------------------------------------------------------------------------------

  244. Start Renaming Generated Instances

  245. ---------------------------------------------------------------------------------

  246. ---------------------------------------------------------------------------------

  247. Finished Renaming Generated Instances : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  248. ---------------------------------------------------------------------------------

  249. ---------------------------------------------------------------------------------

  250. Start Rebuilding User Hierarchy

  251. ---------------------------------------------------------------------------------

  252. ---------------------------------------------------------------------------------

  253. Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  254. ---------------------------------------------------------------------------------

  255. ---------------------------------------------------------------------------------

  256. Start Renaming Generated Ports

  257. ---------------------------------------------------------------------------------

  258. ---------------------------------------------------------------------------------

  259. Finished Renaming Generated Ports : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  260. ---------------------------------------------------------------------------------

  261. ---------------------------------------------------------------------------------

  262. Start Handling Custom Attributes

  263. ---------------------------------------------------------------------------------

  264. ---------------------------------------------------------------------------------

  265. Finished Handling Custom Attributes : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  266. ---------------------------------------------------------------------------------

  267. ---------------------------------------------------------------------------------

  268. Start Renaming Generated Nets

  269. ---------------------------------------------------------------------------------

  270. ---------------------------------------------------------------------------------

  271. Finished Renaming Generated Nets : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  272. ---------------------------------------------------------------------------------

  273. ---------------------------------------------------------------------------------

  274. Start Writing Synthesis Report

  275. ---------------------------------------------------------------------------------

  276. 

  277. Report BlackBoxes: 

  278. +-+--------------+----------+

  279. | |BlackBox name |Instances |

  280. +-+--------------+----------+

  281. +-+--------------+----------+

  282. 

  283. Report Cell Usage: 

  284. +------+--------+------+

  285. |      |Cell    |Count |

  286. +------+--------+------+

  287. |1     |BUFG    |     1|

  288. |2     |CARRY4  |  1613|

  289. |3     |DSP48E1 |    13|

  290. |4     |LUT1    |   165|

  291. |5     |LUT2    |  1000|

  292. |6     |LUT3    |  2638|

  293. |7     |LUT4    |  2484|

  294. |8     |LUT5    |   799|

  295. |9     |LUT6    |  3246|

  296. |10    |FDRE    |   128|

  297. |11    |IBUF    |   159|

  298. |12    |OBUF    |    64|

  299. +------+--------+------+

  300. ---------------------------------------------------------------------------------

  301. Finished Writing Synthesis Report : Time (s): cpu = 00:00:50 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  302. ---------------------------------------------------------------------------------

  303. Synthesis finished with 0 errors, 0 critical warnings and 11 warnings.

  304. Synthesis Optimization Runtime : Time (s): cpu = 00:00:41 ; elapsed = 00:00:49 . Memory (MB): peak = 1517.203 ; gain = 243.609

  305. Synthesis Optimization Complete : Time (s): cpu = 00:00:51 ; elapsed = 00:00:51 . Memory (MB): peak = 1517.203 ; gain = 256.160

  306. INFO: [Project 1-571] Translating synthesized netlist

  307. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.125 . Memory (MB): peak = 1517.203 ; gain = 0.000

  308. INFO: [Netlist 29-17] Analyzing 1626 Unisim elements for replacement

  309. INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds

  310. WARNING: [Netlist 29-101] Netlist 'regler' is not ideal for floorplanning, since the cellview 'regler' contains a large number of primitives.  Please consider enabling hierarchy in synthesis if you want to do floorplanning.

  311. INFO: [Project 1-570] Preparing netlist for logic optimization

  312. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).

  313. Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1517.203 ; gain = 0.000

  314. INFO: [Project 1-111] Unisim Transformation Summary:

  315. No Unisim elements were transformed.

  316. 

  317. Synth Design complete, checksum: b5ea81b7

  318. INFO: [Common 17-83] Releasing license: Synthesis

  319. 21 Infos, 26 Warnings, 0 Critical Warnings and 0 Errors encountered.

  320. synth_design completed successfully

  321. synth_design: Time (s): cpu = 00:00:58 ; elapsed = 00:00:59 . Memory (MB): peak = 1517.203 ; gain = 256.160

  322. INFO: [Common 17-1381] The checkpoint 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp' has been generated.

  323. INFO: [runtcl-4] Executing : report_utilization -file regler_utilization_synth.rpt -pb regler_utilization_synth.pb

  324. INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:59:52 2022...