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- Vivado Simulator v2021.2
- Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.
- Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log
- Using 2 slave threads.
- Starting static elaboration
- Completed static elaboration
- Starting simulation data flow analysis
- Completed simulation data flow analysis
- Time Resolution for simulation is 1ps
- Compiling package std.standard
- Compiling package std.textio
- Compiling package ieee.std_logic_1164
- Compiling package ieee.numeric_std
- Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]
- Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]
- Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db
- Built simulation snapshot pwm_test_db_behav
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