FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsim.rlx

{ 
    crc :  6733451111524596900  , 
    ccp_crc :  0  , 
    cmdline : " --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db" , 
    buildDate : "Oct 19 2021" , 
    buildTime : "03:16:22" , 
    linkCmd : "C:\\Xilinx\\Vivado\\2021.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W  -O -Wl,--stack,104857600 -o \"xsim.dir/pwm_test_db_behav/xsimk.exe\"   \"xsim.dir/pwm_test_db_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pwm_test_db_behav/obj/xsim_1.win64.obj\" -L\"C:\\Xilinx\\Vivado\\2021.2\\lib\\win64.o\" -lrdi_simulator_kernel   -lrdi_simbridge_kernel" , 
    aggregate_nets : 
    [ 
    ] 
}