FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini

[General]
ARRAY_DISPLAY_LIMIT=1024
RADIX=hex
TIME_UNIT=ns
TRACE_LIMIT=65536
VHDL_ENTITY_SCOPE_FILTER=true
VHDL_PACKAGE_SCOPE_FILTER=false
VHDL_BLOCK_SCOPE_FILTER=true
VHDL_PROCESS_SCOPE_FILTER=false
VHDL_PROCEDURE_SCOPE_FILTER=false
VERILOG_MODULE_SCOPE_FILTER=true
VERILOG_PACKAGE_SCOPE_FILTER=false
VERILOG_BLOCK_SCOPE_FILTER=false
VERILOG_TASK_SCOPE_FILTER=false
VERILOG_PROCESS_SCOPE_FILTER=false
INPUT_OBJECT_FILTER=true
OUTPUT_OBJECT_FILTER=true
INOUT_OBJECT_FILTER=true
INTERNAL_OBJECT_FILTER=true
CONSTANT_OBJECT_FILTER=true
VARIABLE_OBJECT_FILTER=true
INPUT_PROTOINST_FILTER=true
OUTPUT_PROTOINST_FILTER=true
INOUT_PROTOINST_FILTER=true
INTERNAL_PROTOINST_FILTER=true
CONSTANT_PROTOINST_FILTER=true
VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=157
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
OBJECT_NAME_COLUMN_WIDTH=156
OBJECT_VALUE_COLUMN_WIDTH=49
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75
FRAME_INDEX_COLUMN_WIDTH=75
FRAME_NAME_COLUMN_WIDTH=75
FRAME_FILE_NAME_COLUMN_WIDTH=75
FRAME_LINE_NUM_COLUMN_WIDTH=156
LOCAL_NAME_COLUMN_WIDTH=49
LOCAL_VALUE_COLUMN_WIDTH=75
LOCAL_DATA_TYPE_COLUMN_WIDTH=0
PROTO_NAME_COLUMN_WIDTH=0
PROTO_VALUE_COLUMN_WIDTH=0
INPUT_LOCAL_FILTER=1
OUTPUT_LOCAL_FILTER=1
INOUT_LOCAL_FILTER=1
INTERNAL_LOCAL_FILTER=1
CONSTANT_LOCAL_FILTER=1
VARIABLE_LOCAL_FILTER=1
[Object Radixes]
RADIX_0=hex /pwm_test_db/cnt;