FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 04/25/2022 01:45:24 PM
-- Design Name: 
-- Module Name: pt1 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pt1 is
  Port ( 
        clk : in STD_LOGIC;
        u : in signed(63 downto 0) := to_signed(0, 64);
        y : inout signed(63 downto 0) := to_signed(0, 64); -- muss vielleicht initalisiert werden vorher!?
        a : in signed(9 downto 0) := to_signed(1, 10);
        k : in signed(9 downto 0) := to_signed(1, 10);
        stepWidth : signed(9 downto 0) := to_signed(10, 10)); --in us -> 10us
end pt1;

architecture Behavioral of pt1 is


--signal stepWidth : integer := 10;       -- in us -> 10 us   später berechnet aus Clk und Prescaler
signal prescaler : signed(63 downto 0) := to_signed(1000000, 64);   -- prescaler für Zeit

-- Konstanten Streckenparameter
--signal a : integer := 1;
--signal k : integer := 1;


-- signal u : integer := 100000; -- Eingangswert Strecke jetzt u aus port
-- signal x : integer := 0; -- Ausgangssignal Strecke -> Stellgröße jetzt y aus port



begin

process(clk)

variable y_var : signed(83 downto 0) := to_signed(0, 84); 

    begin
        if rising_edge(clk) then
            y_var := y + stepWidth * (k * u - a * y) / prescaler; -- durch 1000 wg. milisekunden abtastzeit  
            y <= y_var(63 downto 0);     
        end if;
        
end process;
end Behavioral;