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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou

vivado.jou 5.2KB
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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Mon May 23 20:31:11 2022

  6. # Process ID: 10504

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

  15. update_compile_order -fileset sources_1

  16. launch_runs synth_1 -jobs 6

  17. wait_on_run synth_1

  18. reset_run synth_1

  19. launch_runs synth_1 -jobs 6

  20. wait_on_run synth_1

  21. reset_run synth_1

  22. launch_runs synth_1 -jobs 6

  23. wait_on_run synth_1

  24. reset_run synth_1

  25. launch_runs synth_1 -jobs 6

  26. wait_on_run synth_1

  27. reset_run synth_1

  28. launch_runs synth_1 -jobs 6

  29. wait_on_run synth_1

  30. reset_run synth_1

  31. launch_runs synth_1 -jobs 6

  32. wait_on_run synth_1

  33. reset_run synth_1

  34. launch_runs synth_1 -jobs 6

  35. wait_on_run synth_1

  36. reset_run synth_1

  37. launch_runs synth_1 -jobs 6

  38. wait_on_run synth_1

  39. reset_run synth_1

  40. launch_runs synth_1 -jobs 6

  41. wait_on_run synth_1

  42. reset_run synth_1

  43. launch_runs synth_1 -jobs 6

  44. wait_on_run synth_1

  45. reset_run synth_1

  46. launch_runs synth_1 -jobs 6

  47. wait_on_run synth_1

  48. reset_run synth_1

  49. launch_runs synth_1 -jobs 6

  50. wait_on_run synth_1

  51. reset_run synth_1

  52. launch_runs synth_1 -jobs 6

  53. wait_on_run synth_1

  54. reset_run synth_1

  55. launch_runs synth_1 -jobs 6

  56. wait_on_run synth_1

  57. reset_run synth_1

  58. launch_runs synth_1 -jobs 6

  59. wait_on_run synth_1

  60. launch_simulation

  61. launch_simulation

  62. launch_simulation

  63. launch_simulation

  64. launch_simulation

  65. launch_simulation

  66. launch_simulation

  67. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  68. source pwm_test_db.tcl

  69. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  70. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  71. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  72. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  73. close_sim

  74. launch_simulation

  75. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  76. source pwm_test_db.tcl

  77. add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64

  78. remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64

  79. add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64

  80. remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64

  81. reset_run synth_1

  82. launch_runs synth_1 -jobs 6

  83. wait_on_run synth_1

  84. close_sim

  85. launch_simulation

  86. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  87. source pwm_test_db.tcl

  88. reset_run synth_1

  89. launch_runs synth_1 -jobs 6

  90. wait_on_run synth_1

  91. close_sim

  92. launch_simulation

  93. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  94. source pwm_test_db.tcl

  95. close_sim