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FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

vivado.log 67KB
Raw Blame History

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  1. #-----------------------------------------------------------

  2. # Vivado v2021.2 (64-bit)

  3. # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021

  4. # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021

  5. # Start of session at: Mon May 23 20:31:11 2022

  6. # Process ID: 10504

  7. # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim

  8. # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent7676 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr

  9. # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log

  10. # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou

  11. # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB

  12. #-----------------------------------------------------------

  13. start_gui

  14. open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr

  15. INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter.

  16. Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim'

  17. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  18. WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  19. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available

  20. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  21. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available

  22. WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available

  23. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available

  24. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available

  25. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  26. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  27. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  28. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available

  29. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available

  30. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  31. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  32. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available

  33. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available

  34. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available

  35. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available

  36. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available

  37. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available

  38. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available

  39. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available

  40. WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available

  41. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available

  42. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  43. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available

  44. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  45. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  46. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available

  47. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  48. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  49. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available

  50. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  51. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  52. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available

  53. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available

  54. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available

  55. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available

  56. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  57. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  58. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available

  59. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available

  60. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available

  61. WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available

  62. INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'.

  63. INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.

  64. Scanning sources...

  65. Finished scanning sources

  66. INFO: [IP_Flow 19-234] Refreshing IP repositories

  67. INFO: [IP_Flow 19-1704] No user IP repositories specified

  68. INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.

  69. open_project: Time (s): cpu = 00:00:26 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000

  70. update_compile_order -fileset sources_1

  71. launch_runs synth_1 -jobs 6

  72. [Mon May 23 20:59:31 2022] Launched synth_1...

  73. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  74. reset_run synth_1

  75. launch_runs synth_1 -jobs 6

  76. [Mon May 23 21:01:23 2022] Launched synth_1...

  77. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  78. reset_run synth_1

  79. launch_runs synth_1 -jobs 6

  80. [Mon May 23 21:13:32 2022] Launched synth_1...

  81. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  82. reset_run synth_1

  83. launch_runs synth_1 -jobs 6

  84. [Mon May 23 21:15:40 2022] Launched synth_1...

  85. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  86. reset_run synth_1

  87. launch_runs synth_1 -jobs 6

  88. [Mon May 23 21:18:26 2022] Launched synth_1...

  89. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  90. reset_run synth_1

  91. launch_runs synth_1 -jobs 6

  92. [Mon May 23 21:20:30 2022] Launched synth_1...

  93. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  94. reset_run synth_1

  95. launch_runs synth_1 -jobs 6

  96. [Mon May 23 21:21:45 2022] Launched synth_1...

  97. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  98. reset_run synth_1

  99. launch_runs synth_1 -jobs 6

  100. [Mon May 23 21:23:09 2022] Launched synth_1...

  101. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  102. reset_run synth_1

  103. launch_runs synth_1 -jobs 6

  104. [Mon May 23 21:24:17 2022] Launched synth_1...

  105. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  106. reset_run synth_1

  107. launch_runs synth_1 -jobs 6

  108. [Mon May 23 21:25:12 2022] Launched synth_1...

  109. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  110. reset_run synth_1

  111. launch_runs synth_1 -jobs 6

  112. [Mon May 23 21:26:12 2022] Launched synth_1...

  113. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  114. reset_run synth_1

  115. launch_runs synth_1 -jobs 6

  116. [Mon May 23 21:27:34 2022] Launched synth_1...

  117. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  118. reset_run synth_1

  119. launch_runs synth_1 -jobs 6

  120. [Mon May 23 22:11:01 2022] Launched synth_1...

  121. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  122. reset_run synth_1

  123. launch_runs synth_1 -jobs 6

  124. [Mon May 23 22:12:13 2022] Launched synth_1...

  125. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  126. reset_run synth_1

  127. launch_runs synth_1 -jobs 6

  128. [Mon May 23 22:14:47 2022] Launched synth_1...

  129. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  130. launch_simulation

  131. Command: launch_simulation 

  132. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  133. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  134. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  135. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  136. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  137. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  138. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  139. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  140. INFO: [USF-XSim-97] Finding global include files...

  141. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  142. INFO: [USF-XSim-2] XSim::Compile design

  143. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  144. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  145. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  146. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  147. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  148. INFO: [VRFC 10-3107] analyzing entity 'regler'

  149. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  150. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  151. ERROR: [VRFC 10-3214] character 'A' is not in element type 'std_ulogic' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:63]

  152. ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43]

  153. INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors

  154. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  155. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log'

  156. ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information.

  157. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  158. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  159. launch_simulation

  160. Command: launch_simulation 

  161. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  162. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  163. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  164. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  165. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  166. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  167. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  168. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  169. INFO: [USF-XSim-97] Finding global include files...

  170. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  171. INFO: [USF-XSim-2] XSim::Compile design

  172. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  173. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  174. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  175. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  176. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  177. INFO: [VRFC 10-3107] analyzing entity 'regler'

  178. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  179. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  180. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  181. INFO: [USF-XSim-3] XSim::Elaborate design

  182. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  183. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  184. Vivado Simulator v2021.2

  185. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  186. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  187. Using 2 slave threads.

  188. Starting static elaboration

  189. ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:50]

  190. ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53]

  191. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.

  192. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  193. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  194. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  195. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  196. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  197. launch_simulation

  198. Command: launch_simulation 

  199. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  200. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  201. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  202. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  203. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  204. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  205. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  206. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  207. INFO: [USF-XSim-97] Finding global include files...

  208. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  209. INFO: [USF-XSim-2] XSim::Compile design

  210. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  211. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  212. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  213. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  214. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  215. INFO: [USF-XSim-3] XSim::Elaborate design

  216. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  217. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  218. Vivado Simulator v2021.2

  219. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  220. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  221. Using 2 slave threads.

  222. Starting static elaboration

  223. ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:42]

  224. ERROR: [VRFC 10-664] expression has 1 elements ; expected 10 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:45]

  225. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.

  226. INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds

  227. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  228. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  229. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  230. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  231. launch_simulation

  232. Command: launch_simulation 

  233. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  234. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  235. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  236. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  237. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  238. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  239. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  240. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  241. INFO: [USF-XSim-97] Finding global include files...

  242. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  243. INFO: [USF-XSim-2] XSim::Compile design

  244. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  245. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  246. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  247. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  248. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  249. INFO: [VRFC 10-3107] analyzing entity 'regler'

  250. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  251. INFO: [USF-XSim-3] XSim::Elaborate design

  252. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  253. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  254. Vivado Simulator v2021.2

  255. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  256. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  257. Using 2 slave threads.

  258. Starting static elaboration

  259. ERROR: [VRFC 10-3311] expression has 10 elements ; formal 'stepwidth' expects 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:110]

  260. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.

  261. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  262. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  263. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  264. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  265. launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1582.152 ; gain = 0.000

  266. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  267. launch_simulation

  268. Command: launch_simulation 

  269. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  270. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  271. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  272. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  273. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  274. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  275. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  276. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  277. INFO: [USF-XSim-97] Finding global include files...

  278. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  279. INFO: [USF-XSim-2] XSim::Compile design

  280. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  281. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  282. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  283. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  284. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  285. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  286. INFO: [USF-XSim-69] 'compile' step finished in '1' seconds

  287. INFO: [USF-XSim-3] XSim::Elaborate design

  288. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  289. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  290. Vivado Simulator v2021.2

  291. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  292. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  293. Using 2 slave threads.

  294. Starting static elaboration

  295. ERROR: [VRFC 10-664] expression has 10 elements ; expected 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:59]

  296. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.

  297. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  298. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  299. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  300. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  301. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  302. launch_simulation

  303. Command: launch_simulation 

  304. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  305. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  306. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  307. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  308. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  309. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  310. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  311. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  312. INFO: [USF-XSim-97] Finding global include files...

  313. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  314. INFO: [USF-XSim-2] XSim::Compile design

  315. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  316. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  317. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  318. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  319. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  320. INFO: [USF-XSim-3] XSim::Elaborate design

  321. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  322. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  323. Vivado Simulator v2021.2

  324. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  325. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  326. Using 2 slave threads.

  327. Starting static elaboration

  328. ERROR: [VRFC 10-664] expression has 10 elements ; expected 64 [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:60]

  329. ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit pwm_test_db in library work failed.

  330. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  331. INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log'

  332. ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information.

  333. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.

  334. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

  335. launch_simulation

  336. Command: launch_simulation 

  337. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  338. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  339. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  340. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  341. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  342. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  343. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  344. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  345. INFO: [USF-XSim-97] Finding global include files...

  346. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  347. INFO: [USF-XSim-2] XSim::Compile design

  348. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  349. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  350. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib

  351. INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db'

  352. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  353. INFO: [USF-XSim-3] XSim::Elaborate design

  354. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  355. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  356. Vivado Simulator v2021.2

  357. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  358. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  359. Using 2 slave threads.

  360. Starting static elaboration

  361. Completed static elaboration

  362. Starting simulation data flow analysis

  363. Completed simulation data flow analysis

  364. Time Resolution for simulation is 1ps

  365. Compiling package std.standard

  366. Compiling package std.textio

  367. Compiling package ieee.std_logic_1164

  368. Compiling package ieee.numeric_std

  369. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  370. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  371. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  372. Built simulation snapshot pwm_test_db_behav

  373. INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds

  374. INFO: [USF-XSim-4] XSim::Simulate design

  375. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  376. INFO: [USF-XSim-98] *** Running xsim

  377.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  378. INFO: [USF-XSim-8] Loading simulator feature

  379. Time resolution is 1 ps

  380. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  381. source pwm_test_db.tcl

  382. # set curr_wave [current_wave_config]

  383. # if { [string length $curr_wave] == 0 } {

  384. #   if { [llength [get_objects]] > 0} {

  385. #     add_wave /

  386. #     set_property needs_save false [current_wave_config]

  387. #   } else {

  388. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  389. #   }

  390. # }

  391. # run 10 s

  392. ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements

  393. Time: 5 us  Iteration: 0  Process: /pwm_test_db/uut_pt1/line__61

  394.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd

  395. 

  396. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64

  397. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  398. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  399. launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:10 . Memory (MB): peak = 1582.152 ; gain = 0.000

  400. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  401. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  402. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  403. save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg}

  404. close_sim

  405. INFO: [Simtcl 6-16] Simulation closed

  406. launch_simulation

  407. Command: launch_simulation 

  408. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  409. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  410. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  411. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  412. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  413. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  414. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  415. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  416. INFO: [USF-XSim-97] Finding global include files...

  417. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  418. INFO: [USF-XSim-2] XSim::Compile design

  419. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  420. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  421. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  422. INFO: [USF-XSim-3] XSim::Elaborate design

  423. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  424. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  425. Vivado Simulator v2021.2

  426. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  427. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  428. Using 2 slave threads.

  429. Starting static elaboration

  430. Completed static elaboration

  431. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  432. INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds

  433. INFO: [USF-XSim-4] XSim::Simulate design

  434. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  435. INFO: [USF-XSim-98] *** Running xsim

  436.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  437. INFO: [USF-XSim-8] Loading simulator feature

  438. Time resolution is 1 ps

  439. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  440. source pwm_test_db.tcl

  441. # set curr_wave [current_wave_config]

  442. # if { [string length $curr_wave] == 0 } {

  443. #   if { [llength [get_objects]] > 0} {

  444. #     add_wave /

  445. #     set_property needs_save false [current_wave_config]

  446. #   } else {

  447. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  448. #   }

  449. # }

  450. # run 10 s

  451. ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements

  452. Time: 5 us  Iteration: 0  Process: /pwm_test_db/uut_pt1/line__61

  453.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd

  454. 

  455. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64

  456. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  457. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  458. launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 1582.152 ; gain = 0.000

  459. add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64

  460. remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64

  461. add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} 64

  462. remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd} -line 64

  463. reset_run synth_1

  464. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  465. WARNING: [Vivado 12-1017] Problems encountered:

  466. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  467. 

  468. launch_runs synth_1 -jobs 6

  469. [Mon May 23 22:30:42 2022] Launched synth_1...

  470. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  471. close_sim

  472. INFO: [Simtcl 6-16] Simulation closed

  473. launch_simulation

  474. Command: launch_simulation 

  475. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  476. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  477. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  478. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  479. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  480. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  481. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  482. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  483. INFO: [USF-XSim-97] Finding global include files...

  484. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  485. INFO: [USF-XSim-2] XSim::Compile design

  486. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  487. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  488. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  489. INFO: [USF-XSim-3] XSim::Elaborate design

  490. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  491. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  492. Vivado Simulator v2021.2

  493. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  494. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  495. Using 2 slave threads.

  496. Starting static elaboration

  497. Completed static elaboration

  498. INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel

  499. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  500. INFO: [USF-XSim-4] XSim::Simulate design

  501. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  502. INFO: [USF-XSim-98] *** Running xsim

  503.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  504. INFO: [USF-XSim-8] Loading simulator feature

  505. Time resolution is 1 ps

  506. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  507. source pwm_test_db.tcl

  508. # set curr_wave [current_wave_config]

  509. # if { [string length $curr_wave] == 0 } {

  510. #   if { [llength [get_objects]] > 0} {

  511. #     add_wave /

  512. #     set_property needs_save false [current_wave_config]

  513. #   } else {

  514. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  515. #   }

  516. # }

  517. # run 10 s

  518. ERROR: Array sizes do not match, left array has 64 elements, right array has 84 elements

  519. Time: 5 us  Iteration: 0  Process: /pwm_test_db/uut_pt1/line__61

  520.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd

  521. 

  522. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:64

  523. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  524. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  525. launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 1582.152 ; gain = 0.000

  526. reset_run synth_1

  527. INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp

  528. WARNING: [Vivado 12-1017] Problems encountered:

  529. 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1

  530. 

  531. launch_runs synth_1 -jobs 6

  532. [Mon May 23 22:43:21 2022] Launched synth_1...

  533. Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log

  534. close_sim

  535. INFO: [Simtcl 6-16] Simulation closed

  536. launch_simulation

  537. Command: launch_simulation 

  538. INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db'

  539. WARNING: [Vivado 12-12986] Compiled library path does not exist: ''

  540. INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  541. INFO: [SIM-utils-51] Simulation object is 'sim_1'

  542. INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0'

  543. INFO: [USF-XSim-7] Finding pre-compiled libraries...

  544. INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  545. INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'...

  546. INFO: [USF-XSim-97] Finding global include files...

  547. INFO: [USF-XSim-98] Fetching design files from 'sim_1'...

  548. INFO: [USF-XSim-2] XSim::Compile design

  549. INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  550. "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj"

  551. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib

  552. INFO: [VRFC 10-3107] analyzing entity 'pt1'

  553. INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib

  554. INFO: [VRFC 10-3107] analyzing entity 'regler'

  555. INFO: [USF-XSim-69] 'compile' step finished in '2' seconds

  556. INFO: [USF-XSim-3] XSim::Elaborate design

  557. INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  558. "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log"

  559. Vivado Simulator v2021.2

  560. Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved.

  561. Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log 

  562. Using 2 slave threads.

  563. Starting static elaboration

  564. Completed static elaboration

  565. Starting simulation data flow analysis

  566. Completed simulation data flow analysis

  567. Time Resolution for simulation is 1ps

  568. Compiling package std.standard

  569. Compiling package std.textio

  570. Compiling package ieee.std_logic_1164

  571. Compiling package ieee.numeric_std

  572. Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default]

  573. Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default]

  574. Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db

  575. Built simulation snapshot pwm_test_db_behav

  576. INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds

  577. INFO: [USF-XSim-4] XSim::Simulate design

  578. INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim'

  579. INFO: [USF-XSim-98] *** Running xsim

  580.    with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}"

  581. INFO: [USF-XSim-8] Loading simulator feature

  582. Time resolution is 1 ps

  583. open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg

  584. source pwm_test_db.tcl

  585. # set curr_wave [current_wave_config]

  586. # if { [string length $curr_wave] == 0 } {

  587. #   if { [llength [get_objects]] > 0} {

  588. #     add_wave /

  589. #     set_property needs_save false [current_wave_config]

  590. #   } else {

  591. #      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."

  592. #   }

  593. # }

  594. # run 10 s

  595. ERROR: Array sizes do not match, left array has 148 elements, right array has 84 elements

  596. Time: 5 us  Iteration: 0  Process: /pwm_test_db/uut_pt1/line__63

  597.   File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd

  598. 

  599. HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd:69

  600. INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded.

  601. INFO: [USF-XSim-97] XSim simulation ran for 10 s

  602. launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1582.152 ; gain = 0.000

  603. close_sim

  604. INFO: [Simtcl 6-16] Simulation closed

  605. exit

  606. INFO: [Common 17-206] Exiting Vivado at Mon May 23 22:51:46 2022...