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FPGA_Projekt_Regler
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FPGA_Projekt_Regler
/
StreckenSim_mitRegler
/
fixedPointTest
/
fixedPointTest.srcs
History
Felix Stamm
0535f1a7ff
Regler und Strecke Zeit neu skaliert, Parameter als inputs ergänzt
2 years ago
..
constrs_1/imports/
digilent-xdc-master
Doku verlinkt
2 years ago
sim_1/
new
Simulator-Datentyp angepasst
2 years ago
sources_1
Regler und Strecke Zeit neu skaliert, Parameter als inputs ergänzt
2 years ago
utils_1/imports/
synth_1
Doku verlinkt
2 years ago