100 changed files with 5725 additions and 3143 deletions
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.cache/wt/project.wpc
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| @@ -1,4 +1,4 @@ | |||
| version:1 | |||
| 57656254616c6b5472616e736d697373696f6e417474656d70746564:13 | |||
| 6d6f64655f636f756e7465727c4755494d6f6465:23 | |||
| 6d6f64655f636f756e7465727c4755494d6f6465:25 | |||
| eof: | |||
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/gen_run.xml
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| @@ -1,14 +1,11 @@ | |||
| <?xml version="1.0" encoding="UTF-8"?> | |||
| <GenRun Id="synth_1" LaunchPart="xc7z010clg400-1" LaunchTime="1652439174" LaunchIncrCheckpoint="$PPRDIR/../../../../../StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp"> | |||
| <File Type="PA-TCL" Name="regler.tcl"/> | |||
| <File Type="RDS-PROPCONSTRS" Name="regler_drc_synth.rpt"/> | |||
| <File Type="REPORTS-TCL" Name="regler_reports.tcl"/> | |||
| <File Type="RDS-RDS" Name="regler.vds"/> | |||
| <File Type="RDS-UTIL" Name="regler_utilization_synth.rpt"/> | |||
| <File Type="RDS-UTIL-PB" Name="regler_utilization_synth.pb"/> | |||
| <File Type="RDS-DCP" Name="regler.dcp"/> | |||
| <File Type="VDS-TIMINGSUMMARY" Name="regler_timing_summary_synth.rpt"/> | |||
| <File Type="VDS-TIMING-PB" Name="regler_timing_summary_synth.pb"/> | |||
| <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1"> | |||
| <Filter Type="Srcs"/> | |||
| <File Path="$PSRCDIR/sources_1/new/pwm_test.vhd"> | |||
+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.bat
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| @@ -6,7 +6,7 @@ REM Filename : compile.bat | |||
| REM Simulator : Xilinx Vivado Simulator | |||
| REM Description : Script for compiling the simulation design source files | |||
| REM | |||
| REM Generated by Vivado on Fri May 13 12:56:52 +0200 2022 | |||
| REM Generated by Vivado on Fri May 13 13:48:21 +0200 2022 | |||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| REM | |||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
+ 0
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/compile.log
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| @@ -1,2 +0,0 @@ | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
+ 1
- 1
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.bat
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| @@ -6,7 +6,7 @@ REM Filename : elaborate.bat | |||
| REM Simulator : Xilinx Vivado Simulator | |||
| REM Description : Script for elaborating the compiled design | |||
| REM | |||
| REM Generated by Vivado on Fri May 13 12:56:53 +0200 2022 | |||
| REM Generated by Vivado on Fri May 13 13:48:23 +0200 2022 | |||
| REM SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| REM | |||
| REM IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log
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| @@ -8,17 +8,4 @@ WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/pwm_test_db_behav.wdb
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BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xelab.pb
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+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimSettings.ini
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| @@ -28,7 +28,7 @@ VARIABLE_PROTOINST_FILTER=true | |||
| SCOPE_NAME_COLUMN_WIDTH=157 | |||
| SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 | |||
| SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 | |||
| OBJECT_NAME_COLUMN_WIDTH=75 | |||
| OBJECT_NAME_COLUMN_WIDTH=156 | |||
| OBJECT_VALUE_COLUMN_WIDTH=75 | |||
| OBJECT_DATA_TYPE_COLUMN_WIDTH=75 | |||
| PROCESS_NAME_COLUMN_WIDTH=75 | |||
+ 3
- 0
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/pwm_test_db_behav/xsimkernel.log
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| @@ -2,3 +2,6 @@ Running: xsim.dir/pwm_test_db_behav/xsimk.exe -simmode gui -wdb pwm_test_db_beha | |||
| Design successfully loaded | |||
| Design Loading Memory Usage: 7256 KB (Peak: 7256 KB) | |||
| Design Loading CPU Usage: 15 ms | |||
| Simulation completed | |||
| Simulation Memory Usage: 7792 KB (Peak: 7792 KB) | |||
| Simulation CPU Usage: 15 ms | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pwm_test_db.vdb
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+ 1
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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| @@ -2,7 +2,7 @@ | |||
| 2020.2 | |||
| Oct 19 2021 | |||
| 03:16:22 | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652439407,vhdl2008,,,,pwm_test_db,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd,1652442389,vhdl,,,,pwm_test_db,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd,1651498208,vhdl,,,,pt1,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd,1652437038,vhdl,,,,regler,,,,,,,, | |||
| C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd,1652437027,vhdl,,,,wendetangente,,,,,,,, | |||
+ 0
- 2
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log
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| @@ -1,2 +0,0 @@ | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
BIN
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.pb
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+ 1
- 1
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd
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| @@ -116,7 +116,7 @@ begin | |||
| cnt <= cnt+1; | |||
| risingEdge <= '1'; | |||
| clk_100 <= '0'; | |||
| a <= a + to_sfixed(1.111, 7, -6); | |||
| --a <= a + to_sfixed(1.111, 7, -6); | |||
| end if; | |||
| if clk = '0' then | |||
+ 2
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr
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| @@ -56,7 +56,7 @@ | |||
| <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> | |||
| <Option Name="EnableBDX" Val="FALSE"/> | |||
| <Option Name="DSABoardId" Val="zybo-z7-10"/> | |||
| <Option Name="WTXSimLaunchSim" Val="116"/> | |||
| <Option Name="WTXSimLaunchSim" Val="119"/> | |||
| <Option Name="WTModelSimLaunchSim" Val="0"/> | |||
| <Option Name="WTQuestaLaunchSim" Val="0"/> | |||
| <Option Name="WTIesLaunchSim" Val="0"/> | |||
| @@ -177,7 +177,7 @@ | |||
| <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1"> | |||
| <Filter Type="Srcs"/> | |||
| <File Path="$PSRCDIR/sim_1/new/pwm_test_db.vhd"> | |||
| <FileInfo SFType="VHDL2008"> | |||
| <FileInfo> | |||
| <Attr Name="UsedIn" Val="synthesis"/> | |||
| <Attr Name="UsedIn" Val="simulation"/> | |||
| </FileInfo> | |||
+ 3
- 67
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.jou
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| @@ -2,10 +2,10 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Start of session at: Fri May 13 14:02:42 2022 | |||
| # Process ID: 17732 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| @@ -13,67 +13,3 @@ | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_simulation | |||
| launch_simulation | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
+ 4
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log
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| @@ -2,10 +2,10 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Start of session at: Fri May 13 14:02:42 2022 | |||
| # Process ID: 17732 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent18808 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| @@ -66,710 +66,5 @@ Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| open_project: Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 1591.184 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 11:34:46 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 11:36:03 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| INFO: [Common 17-41] Interrupt caught. Command should exit soon. | |||
| INFO: [Common 17-344] 'source' was cancelled | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| INFO: [BD 41-1808] Open Block Design has been cancelled. | |||
| INFO: [Common 17-344] 'open_bd_design' was cancelled | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:17:21 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 12:18:35 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd> | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:28:24 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl" into library ieee_proposed | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'wendeTangente' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff914b26443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff914b29088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff9180a6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff9180a9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| launch_simulation: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| pwm_test_db_func_synth.wcfg | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '2' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:52:54 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:46] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:53] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:65] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:66] | |||
| ERROR: [VRFC 10-2989] 'std_logic' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:72] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:83] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:90] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:102] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:116] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:117] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "and" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:114] | |||
| ERROR: [VRFC 10-2989] 'risingedge' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:122] | |||
| ERROR: [VRFC 10-2989] 'clk' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2123] 0 definitions of operator "??" match here [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:121] | |||
| ERROR: [VRFC 10-2989] 'clk_100' is not declared [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:126] | |||
| ERROR: [VRFC 10-3782] unit 'behavioral' ignored due to previous errors [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd:43] | |||
| INFO: [VRFC 10-3070] VHDL file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd' ignored due to errors | |||
| INFO: [USF-XSim-69] 'compile' step finished in '3' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' | |||
| ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/xvhdl.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling package ieee.numeric_std | |||
| Compiling package ieee.fixed_float_types | |||
| Compiling package ieee.fixed_pkg | |||
| Compiling package ieee.math_real | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.wendeTangente [wendetangente_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| ERROR: Array sizes do not match, left array has 14 elements, right array has 15 elements | |||
| Time: 0 ps Iteration: 0 Process: /pwm_test_db/uutWendeTangente/line__51 | |||
| File: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| HDL Line: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd:55 | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
+ 0
- 14
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.jou
View File
| @@ -1,14 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Wed May 4 17:41:44 2022 | |||
| # Process ID: 17388 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
+ 16
- 0
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.jou
View File
| @@ -0,0 +1,16 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 13:47:22 2022 | |||
| # Process ID: 19540 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_17388.backup.log → StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_19540.backup.log
View File
| @@ -2,21 +2,24 @@ | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Wed May 4 17:41:44 2022 | |||
| # Process ID: 17388 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent22812 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Start of session at: Fri May 13 13:47:22 2022 | |||
| # Process ID: 19540 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent17020 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #-----------------------------------------------------------sstart_guiopen_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WWARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| @@ -56,12 +59,71 @@ WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 avai | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not availableIINFO: [Project 1-313] Project file moved from 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' since last save.INFO: [filemgmt 56-2] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1', nor could it be found using path 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| IINFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found.Scanning sources... | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| IINFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'.open_project: Time (s): cpu = 00:00:36 ; elapsed = 00:00:19 . Memory (MB): peak = 1250.172 ; gain = 0.000 | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:35 ; elapsed = 00:00:15 . Memory (MB): peak = 1251.859 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [USF-XSim-69] 'compile' step finished in '1' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L ieee_proposed -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:62] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:63] | |||
| WARNING: [VRFC 10-3813] value in initialization depends on signal 'kr' [C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd:64] | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received. | |||
| Printing stacktrace... | |||
| [0] (KiUserExceptionDispatcher+0x2e) [0x7ff9fff076fe] | |||
| [1] (ISIMC::VhdlCompiler::elaborate+0x26ad) [0x7ff65f66946d] | |||
| [2] (ISIMC::VhdlCompiler::saveParserDump+0x1300c) [0x7ff65f67e3fc] | |||
| [3] (ISIMC::VhdlCompiler::saveParserDump+0xfd42) [0x7ff65f67b132] | |||
| [4] (ISIMC::VhdlCompiler::saveParserDump+0xaaea) [0x7ff65f675eda] | |||
| [5] (Verific::VhdlVisitor::TraverseArray+0x43) [0x7ff90fea6443] | |||
| [6] (Verific::VhdlVisitor::Visit+0x48) [0x7ff90fea9088] | |||
| [7] (ISIMC::VhdlCompiler::saveParserDump+0x9cce) [0x7ff65f6750be] | |||
| [8] (ISIMC::VhdlCompiler::saveParserDump+0x9d42) [0x7ff65f675132] | |||
| [9] (ISIMC::VhdlCompiler::saveParserDump+0x15d15) [0x7ff65f681105] | |||
| [10] (ISIMC::VhdlCompiler::saveParserDump+0xb900) [0x7ff65f676cf0] | |||
| [11] (ISIMC::VhdlCompiler::saveParserDump+0x15639) [0x7ff65f680a29] | |||
| [12] (ISIMC::VhdlCompiler::buildSDG+0x1c5) [0x7ff65f6642d5] | |||
| [13] [0x7ff65f3a24cf] | |||
| [14] (boost::serialization::singleton_module::unlock+0x45f7) [0x7ff65f3b9457] | |||
| [15] (boost::serialization::singleton_module::unlock+0x256e) [0x7ff65f3b73ce] | |||
| [16] (boost::archive::detail::iserializer<boost::archive::binary_iarchive,ModuleSerialization>::load_object_data+0x168481c) [0x7ff66102f31c] | |||
| [17] (BaseThreadInitThunk+0x10) [0x7ff9febd54e0] | |||
| Done | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-99] Step results log file:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' | |||
| ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim/elaborate.log' file for more information. | |||
| ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. | |||
| ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. | |||
| exit | |||
| INFO: [Common 17-206] Exiting Vivado at Wed May 4 17:58:54 2022... | |||
| INFO: [Common 17-206] Exiting Vivado at Fri May 13 13:50:06 2022... | |||
+ 0
- 43
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.jou
View File
| @@ -1,43 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Mon May 2 13:48:39 2022 | |||
| # Process ID: 3460 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
+ 0
- 295
StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_3460.backup.log
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| @@ -1,295 +0,0 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Mon May 2 13:48:39 2022 | |||
| # Process ID: 3460 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent9928 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:31 ; elapsed = 00:00:12 . Memory (MB): peak = 1254.516 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '4' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1271.582 ; gain = 17.066 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 13:54:34 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 61 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} -line 62 | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd} 62 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 14:46:17 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pwm_test_db' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| WARNING: [Simulator 45-24] Previous breakpoint at line 62 in file 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd' not restored because it is no longer a breakable line. | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| WARNING: [Vivado 12-1017] Problems encountered: | |||
| 1. Failed to delete one or more files in run directory C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| [Mon May 2 14:59:49 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'pt1' | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pwm_test.vhd" into library xil_defaultlib | |||
| INFO: [VRFC 10-3107] analyzing entity 'regler' | |||
| INFO: [USF-XSim-69] 'compile' step finished in '2' seconds | |||
| INFO: [USF-XSim-3] XSim::Elaborate design | |||
| INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xelab --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log" | |||
| Vivado Simulator v2021.2 | |||
| Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. | |||
| Running: C:/Xilinx/Vivado/2021.2/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L secureip -L xpm --snapshot pwm_test_db_behav xil_defaultlib.pwm_test_db -log elaborate.log | |||
| Using 2 slave threads. | |||
| Starting static elaboration | |||
| Completed static elaboration | |||
| Starting simulation data flow analysis | |||
| Completed simulation data flow analysis | |||
| Time Resolution for simulation is 1ps | |||
| Compiling package std.standard | |||
| Compiling package std.textio | |||
| Compiling package ieee.std_logic_1164 | |||
| Compiling architecture behavioral of entity xil_defaultlib.regler [regler_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pt1 [pt1_default] | |||
| Compiling architecture behavioral of entity xil_defaultlib.pwm_test_db | |||
| Built simulation snapshot pwm_test_db_behav | |||
| INFO: [USF-XSim-69] 'elaborate' step finished in '3' seconds | |||
| INFO: [USF-XSim-4] XSim::Simulate design | |||
| INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [USF-XSim-98] *** Running xsim | |||
| with args "pwm_test_db_behav -key {Behavioral:sim_1:Functional:pwm_test_db} -tclbatch {pwm_test_db.tcl} -view {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} -log {simulate.log}" | |||
| INFO: [USF-XSim-8] Loading simulator feature | |||
| Time resolution is 1 ps | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| # set curr_wave [current_wave_config] | |||
| # if { [string length $curr_wave] == 0 } { | |||
| # if { [llength [get_objects]] > 0} { | |||
| # add_wave / | |||
| # set_property needs_save false [current_wave_config] | |||
| # } else { | |||
| # send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." | |||
| # } | |||
| # } | |||
| # run 5 s | |||
| INFO: [USF-XSim-96] XSim completed. Design snapshot 'pwm_test_db_behav' loaded. | |||
| INFO: [USF-XSim-97] XSim simulation ran for 5 s | |||
| launch_simulation: Time (s): cpu = 00:00:05 ; elapsed = 00:00:09 . Memory (MB): peak = 1271.582 ; gain = 0.000 | |||
| close_sim | |||
| INFO: [Simtcl 6-16] Simulation closed | |||
| exit | |||
| INFO: [Common 17-206] Exiting Vivado at Mon May 2 15:30:20 2022... | |||
+ 83
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| @@ -0,0 +1,83 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_runs impl_1 -jobs 6 | |||
| wait_on_run impl_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| launch_simulation | |||
| launch_simulation | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/a}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/b}} | |||
| current_wave_config {pwm_test_db_func_synth.wcfg} | |||
| add_wave {{/pwm_test_db/uutWendeTangente/c}} | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| add_bp {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} 55 | |||
| remove_bps -file {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd} -line 55 | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| close_sim | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| save_wave_config {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg} | |||
| reset_run synth_1 | |||
| launch_runs synth_1 -jobs 6 | |||
| wait_on_run synth_1 | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
| open_wave_config C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/pwm_test_db_func_synth.wcfg | |||
| source pwm_test_db.tcl | |||
| set_property file_type VHDL [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sim_1/new/pwm_test_db.vhd] | |||
| close_sim | |||
| launch_simulation | |||
| launch_simulation | |||
+ 900
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StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado_5492.backup.log
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| @@ -0,0 +1,900 @@ | |||
| #----------------------------------------------------------- | |||
| # Vivado v2021.2 (64-bit) | |||
| # SW Build 3367213 on Tue Oct 19 02:48:09 MDT 2021 | |||
| # IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 | |||
| # Start of session at: Fri May 13 11:33:33 2022 | |||
| # Process ID: 5492 | |||
| # Current directory: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim | |||
| # Command line: vivado.exe -gui_launcher_event rodinguilauncherevent14532 C:\Users\Felix\OneDrive\Master\Projektarbeit_FPGA\Programme\Git_Projekte\FPGA_Projekt_Regler\StreckenSim_mitRegler\StreckeSim_counter_working\StreckeSim\Coraz7_Test.xpr | |||
| # Log file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/vivado.log | |||
| # Journal file: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim\vivado.jou | |||
| # Running On: DESKTOP-PAACOM8, OS: Windows, CPU Frequency: 2592 MHz, CPU Physical cores: 6, Host memory: 16927 MB | |||
| #----------------------------------------------------------- | |||
| start_gui | |||
| open_project C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.xpr | |||
| INFO: [ProjectBase 1-489] The host OS only allows 260 characters in a normal path. The project is stored in a path with more than 80 characters. If you experience issues with IP, Block Designs, or files not being found, please consider moving the project to a location with a shorter path. Alternately consider using the OS subst command to map part of the path to a drive letter. | |||
| Current project path is 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim' | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:genesys2:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/genesys2/H/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part digilentinc.com:sword:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/boards/board_files/sword/C.0/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/es/1.3/board.xml as part xcvc1902-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_es:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/es/1.3/board.xml as part xcvm1802-vsva2197-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/es/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.0/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.1/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/es/1.2/board.xml as part xczu48dr-fsvg1517-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/es/1.0/board.xml as part xczu58dr-fsvg1517-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.0/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.1 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.1/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216_es:part0:1.2 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/es/1.2/board.xml as part xczu49dr-ffvf1760-2-e-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld_es:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/es/1.0/board.xml as part xczu59dr-ffvf1760-2-i-es1 specified in board_part file is either invalid or not available | |||
| WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:1.0 available at C:/Xilinx/Vivado/2021.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/1.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available | |||
| INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1'. | |||
| INFO: [BD 41-2613] The output directory c:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.gen/sources_1/bd/design_1 for design_1 cannot be found. | |||
| Scanning sources... | |||
| Finished scanning sources | |||
| INFO: [IP_Flow 19-234] Refreshing IP repositories | |||
| INFO: [IP_Flow 19-1704] No user IP repositories specified | |||
| INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2021.2/data/ip'. | |||
| open_project: Time (s): cpu = 00:00:28 ; elapsed = 00:00:10 . Memory (MB): peak = 1580.359 ; gain = 0.000 | |||
| update_compile_order -fileset sources_1 | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 11:34:46 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 11:36:03 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| close [ open C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd w ] | |||
| add_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/wendeTangente.vhd | |||
| update_compile_order -fileset sources_1 | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| INFO: [Common 17-41] Interrupt caught. Command should exit soon. | |||
| INFO: [Common 17-344] 'source' was cancelled | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| ERROR: [Ip 78-89] Error in evaluating command source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl] | |||
| - | |||
| while executing | |||
| "source [rdi::utils::find_approot_file scripts/xguifrmwork/init.tcl]" | |||
| ERROR: [Ip 78-89] Error in evaluating command source init.tcl | |||
| - | |||
| while executing | |||
| "source init.tcl" | |||
| 1 | |||
| INFO: [BD 41-1808] Open Block Design has been cancelled. | |||
| INFO: [Common 17-344] 'open_bd_design' was cancelled | |||
| import_files -norecurse {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_float_types.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg.vhdl C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Bibliotheken/fixedPoint/fixed_generic_pkg-body.vhdl} | |||
| update_compile_order -fileset sources_1 | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_float_types.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_pkg.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg-body.vhdl] | |||
| set_property file_type {VHDL 2008} [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| set_property library ieee_proposed [get_files C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/imports/fixedPoint/fixed_generic_pkg.vhdl] | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:17:21 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_runs impl_1 -jobs 6 | |||
| [Fri May 13 12:18:35 2022] Launched impl_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/impl_1/runme.log | |||
| open_bd_design {C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd} | |||
| Reading block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd>... | |||
| Successfully read diagram <design_1> from block design file <C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/bd/design_1/design_1.bd> | |||
| reset_run synth_1 | |||
| INFO: [Project 1-1161] Replacing file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/utils_1/imports/synth_1/regler.dcp with file C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/regler.dcp | |||
| launch_runs synth_1 -jobs 6 | |||
| [Fri May 13 12:28:24 2022] Launched synth_1... | |||
| Run output will be captured here: C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.runs/synth_1/runme.log | |||
| launch_simulation | |||
| Command: launch_simulation | |||
| INFO: [Vivado 12-12493] Simulation top is 'pwm_test_db' | |||
| WARNING: [Vivado 12-12986] Compiled library path does not exist: '' | |||
| INFO: [Vivado 12-5682] Launching behavioral simulation in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-51] Simulation object is 'sim_1' | |||
| INFO: [SIM-utils-72] Using boost library from 'C:/Xilinx/Vivado/2021.2/tps/boost_1_72_0' | |||
| INFO: [USF-XSim-7] Finding pre-compiled libraries... | |||
| INFO: [USF-XSim-11] File 'C:/Xilinx/Vivado/2021.2/data/xsim/xsim.ini' copied to run dir:'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| INFO: [SIM-utils-54] Inspecting design source files for 'pwm_test_db' in fileset 'sim_1'... | |||
| INFO: [USF-XSim-97] Finding global include files... | |||
| INFO: [USF-XSim-98] Fetching design files from 'sim_1'... | |||
| INFO: [USF-XSim-2] XSim::Compile design | |||
| INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.sim/sim_1/behav/xsim' | |||
| "xvhdl --incr --relax -prj pwm_test_db_vhdl.prj" | |||
| INFO: [VRFC 10-163] Analyzing VHDL file "C:/Users/Felix/OneDrive/Master/Projektarbeit_FPGA/Programme/Git_Projekte/FPGA_Projekt_Regler/StreckenSim_mitRegler/StreckeSim_counter_working/StreckeSim/Coraz7_Test.srcs/sources_1/new/pt1.vhd" into library xil_defaultlib | |||