FPGA_Projekt_Regler/StreckenSim_mitRegler/fixedPointTest/fixedPointTest.runs/impl_1/fixedPointTest_control_sets_placed.rpt

Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.2 (win64) Build 3367213 Tue Oct 19 02:48:09 MDT 2021
| Date         : Fri May 13 14:41:53 2022
| Host         : DESKTOP-PAACOM8 running 64-bit major release  (build 9200)
| Command      : report_control_sets -verbose -file fixedPointTest_control_sets_placed.rpt
| Design       : fixedPointTest
| Device       : xc7z010
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |     0 |
|    Minimum number of control sets                        |     0 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |     0 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |     0 |
| >= 0 to < 4        |     0 |
| >= 4 to < 6        |     0 |
| >= 6 to < 8        |     0 |
| >= 8 to < 10       |     0 |
| >= 10 to < 12      |     0 |
| >= 12 to < 14      |     0 |
| >= 14 to < 16      |     0 |
| >= 16              |     0 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               0 |            0 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |               0 |            0 |
| Yes          | No                    | No                     |               0 |            0 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |               0 |            0 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------+---------------+------------------+------------------+----------------+--------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------+---------------+------------------+------------------+----------------+--------------+